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me.arunkumars
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Registered: ‎10-03-2011

passing verilog parameters from commandline

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Hi

I want to pass verilog parameters from commandline while synthesizing. In NCSIM we can pass the parameter using -DEFPARAM directive.

 

I want to know if there is any method to do same thing in Xilinx-XST also.

 

Thanks in advance

Arunk

 

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ywu
Xilinx Employee
Xilinx Employee
19,887 Views
Registered: ‎11-28-2007

My apologies. I read your email too quickly. To pass parameters (Verilog) or generic (VHDL), you can use the -generics option, which is also documented in the XST UG.

 

 

Cheers,
Jim

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ywu
Xilinx Employee
Xilinx Employee
15,063 Views
Registered: ‎11-28-2007

Take a look at the XST UG below and search for "-define". (By the way, download Xilinx Document Navigator to manage/read all Xilinx documents) :

 

http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/xst.pdf

 


@me.arunkumars wrote:

Hi

I want to pass verilog parameters from commandline while synthesizing. In NCSIM we can pass the parameter using -DEFPARAM directive.

 

I want to know if there is any method to do same thing in Xilinx-XST also.

 

Thanks in advance

Arunk

 




Cheers,
Jim
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me.arunkumars
Visitor
Visitor
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Registered: ‎10-03-2011


"-define" redefines Verilog Macros not parameters. For example in below case i want to pass the PORT and WIDTH from command-line for which i run xst with
CASE1:

-define {PORT=128 WIDTH=7}

module m_name#(
    parameter PORT=64,
    parameter WIDTH=6
)(
    input [PORT-1:0] data_in,
    input [WIDTH-1:0] addr
.
.
.
endmodule
//On compilation the defined values won't reflect in the netlist PORT=64 WIDTH=6 will only reflect

However there is a way to change the parameter i.e. by assigning it to a Verilog macro in the following manner
CASE2:

-define {PORT_NUMBER=128 WIDTH=7}

module m_name#(
    parameter PORT=`PORT_NUMBER,
    parameter WIDTH=`ADDR_WIDTH
)(
    input [PORT-1:0] data_in,
    input [WIDTH-1:0] addr
.
.
.
endmodule


In case2 the parameter will be changed but the above technique has two problems
1.  Suppose there is are two instances of module m_name namely INSTA, INSTB with different PORT and WIDTH values then it wont be possible to change the the instance values uniquely.
2. If there are multiple modules in the design say m_name, m_name1 with same MACRO then it is not possible to maintain different values for them.

  For the above case the design has to be rewritten. Else if defparam is supported then INST.param=val will solve the issue.

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ywu
Xilinx Employee
Xilinx Employee
19,888 Views
Registered: ‎11-28-2007

My apologies. I read your email too quickly. To pass parameters (Verilog) or generic (VHDL), you can use the -generics option, which is also documented in the XST UG.

 

 

Cheers,
Jim

View solution in original post

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me.arunkumars
Visitor
Visitor
15,046 Views
Registered: ‎10-03-2011

That was helpful but that didn't solve the problem fully. "-generics" replaces the parameters in submodules also.

Ex.

note: both top-level and sub-module have same parameter names which is generally the case

module top_lvl#(
    parameter DATA_WIDTH=36,
    parameter ADDR_WIDTH=9
)(...);
...
generate
genvar i;
for (i=0;i<DATA_WIDTH/36;i=i+1)
begin:gen_ram
    block_ram #(.DATA_WIDTH(36), .ADDR_WIDTH(ADDR_WIDTH)) U_blk_ram ( ...);
end
.
.
endmodule

module block_ram #(
    parameter DATA_WIDTH=36,
    parameter ADDR_WIDTH=9
)(...);
endmodule

In the above case using "-generics{DATA_WIDTH=72 ADDR_WIDTH=9}" will instantiate two block rams with DATA_WIDTH 72 which is not desired. Is there is any way i can just declare the
1. top level parameters only
2. parameters of a particular instance only

Thanks Again
Arunk

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markcurry
Scholar
Scholar
15,039 Views
Registered: ‎09-16-2009

Arunk,

 

Double check those results.  The -generics switch should only set the parameters of the top level module.  If it's doing otherwise, that's a very bad thing, and you should open a webcase.  It should NOT do that.

 

--Mark

 

 

 

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me.arunkumars
Visitor
Visitor
15,026 Views
Registered: ‎10-03-2011

Sorry that was my mistake. "-generics" changes the top-levels parameters only.

That solved my problem at top-level.

 

Thanks a bunch

Arunk

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