cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
4,030 Views
Registered: ‎01-22-2015

pipeline to improve performance

Jump to solution

On page 12 of ug474(7-Series CLBs) under Recommended Design Flow it says,  "Flip-flops are abundant. Pipelining should be considered to improve performance."

 

Can someone add explanation to this recommendation from ug474?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Teacher
Teacher
6,892 Views
Registered: ‎03-31-2012

Re: pipeline to improve performance

Jump to solution

markg@prosensing.com

 

>>  "Pipelining is a generally a good thing and tends to use up lots of flip-flops.  However, the FPGA has lots of flip-flops.  So, go ahead and pipeline all you want."

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

0 Kudos
4 Replies
Highlighted
Advisor
Advisor
4,006 Views
Registered: ‎04-26-2015

Re: pipeline to improve performance

Jump to solution

Are you looking for a basic explanation of what pipelining is? The Wikipedia article isn't bad. I'm not sure that it'd make sense to include it in UG474; a separate XAPP might make more sense.

0 Kudos
Highlighted
Teacher
Teacher
3,999 Views
Registered: ‎03-31-2012

Re: pipeline to improve performance

Jump to solution

markg@prosensing.com this recommendation should be followed only if you can afford the latency pipelining will introduce. To wit:

 

pipelining is using registers to store intermediate outputs so that each piece of logic can be run at a higher frequency. Assuming you can overlap all the stages of the pipeline and you can run the pipeline long enough without needing the output and without having to flush it, what you will get is an N times performance increase if you divide the logic into N pipeline stages.

 

Suppose you have M multipliers in series in a calculation. If you build this logic sequentially, your period will be T >= M*Tm when Tm is the period of a single multiplier. On the other hand if you register the output of each multiplier your period will be T >= Tm (ie M times smaller ie M times faster clock) but the first output will come M cycles later and there will be one output every cycle after that. But you will have to keep feeding the pipeline to get this benefit. Assuming number of inputs N >> M, then this is a great benefit.

 

Again this assumes you can tolerate the M cycle wait and also assumes that your logic doesn't have feedback ie you don't need the output coming back to your input at any time.

 

This works well for feedforward logic circuits and large datapath but sometime not so well for control logic where there is feedback in the loop. Another example is signal processing (ala IIR filters) which are difficult to pipeline for this reason. Of course adding latency makes your feedback loops less stable and reduces the bandwidth of the control too.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
Highlighted
3,991 Views
Registered: ‎01-22-2015

Re: pipeline to improve performance

Jump to solution

  and muzaffer 

Thanks for your polite replies to my vague question. 

 

I am familiar with pipelining and its benefits/drawbacks.  -but much appreciate the review by muzaffer.

 

I was reading about CLBs and SLICEs in ug474 when I ran across the comment in question.  The comment seemed out of place but then I thought it might have deep cosmic meaning.

 

Do you think the comment could be interpreted as follows?

"Pipelining is a generally a good thing and tends to use up lots of flip-flops.  However, the FPGA has lots of flip-flops.  So, go ahead and pipeline all you want."

0 Kudos
Highlighted
Teacher
Teacher
6,893 Views
Registered: ‎03-31-2012

Re: pipeline to improve performance

Jump to solution

markg@prosensing.com

 

>>  "Pipelining is a generally a good thing and tends to use up lots of flip-flops.  However, the FPGA has lots of flip-flops.  So, go ahead and pipeline all you want."

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

View solution in original post

0 Kudos