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Visitor morhaf_jaela
Visitor
488 Views
Registered: ‎02-08-2018

pipeling_Encryption_feistel structure

Hello everyone!

I need to implement this figure.

 

the input is divided into two parts ( feistel structure ) and we make some operation on only one part. After that we swap between these parts.

this process will repeat for 68 times ( 0 to 67 ).

 

actually the function of this figure is : 

for i = 0..67
tmp  <= x;
x <= y xor ( x<<1 & x<<8 ) xor x<<2  xor k[i];
y <= tmp ;
end for;

 

the two registers (REG1 and REG2 )to increase the performance.

 

 

I have tired to implement it in VHDL, but i can't!

 

any one can help!

 

encryp.PNG

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1 Reply
Voyager
Voyager
392 Views
Registered: ‎06-20-2017

Re: pipeling_Encryption_feistel structure

What do you mean by '&'?  Do you mean AND, or concatenate?

Adaptable Processing coming to an IP address near you.
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