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maharjanmilan
Participant
Participant
8,535 Views
Registered: ‎07-11-2009

problem in synthesis

Hi,

      I got some vhdl netlists generated from the system generator which I instantiated in VHDL top level module in Xilinx ISE. When I tried to synthesize it, I got the following error

 

ERROR:Xst:1617 - Processing TIMESPEC TS_ce_32_01eb34ed_group_to_ce_32_01eb34ed_group: user TIMEGRP 'ce_32_01eb34ed_group' must be previously defined in FROM/TO constraint.
ERROR:Xst:1489 - Constraint annotation failed.

 

    I need help to resolve this issue.

 

 

Milan

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8 Replies
drjohnsmith
Teacher
Teacher
8,528 Views
Registered: ‎07-09-2009

Hi

 

well it's a timing error, 

 

If it's not in your UCF file

 

 

take a look here, it looks a similar problem

 

http://forums.xilinx.com/xlnx/board/message?message.uid=17142

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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ywu
Xilinx Employee
Xilinx Employee
8,517 Views
Registered: ‎11-28-2007

Which version of ISE are you using? How is the sysgen design integrated with your top level module (do you include .sgp in your ISE project? or do you include the generated VHDL source directly? do you treat it as a blackbox and then include the sysgen .ngc file for your build?)? It would be helpful to attach the your complete project? or at least attach the full synthesis report?

 

Cheers,

Jim

 

Cheers,
Jim
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maharjanmilan
Participant
Participant
8,509 Views
Registered: ‎07-11-2009

Hi Jim,

           I'm using ISE 10.1.03(nt)  version targeting V2Pro30 board. Yes, I included .sgp file in my top level ISE project. Is it possible to include the generated VHDL source directly also and synthesize it ?  What will be the difference? Here are the errors that I got,

 

ERROR:Xst:1617 - Processing TIMESPEC TS_ce_32_8de495df_group_to_ce_32_8de495df_group: user TIMEGRP 'ce_32_8de495df_group' must be previously defined in FROM/TO constraint.
ERROR:Xst:1489 - Constraint annotation failed.
ERROR:Xst:1617 - Processing TIMESPEC TS_ce_32_34914de7_group_to_ce_32_34914de7_group: user TIMEGRP 'ce_32_34914de7_group' must be previously defined in FROM/TO constraint.
ERROR:Xst:1489 - Constraint annotation failed.
ERROR:Xst:1617 - Processing TIMESPEC TS_ce_32_01eb34ed_group_to_ce_32_01eb34ed_group: user TIMEGRP 'ce_32_01eb34ed_group' must be previously defined in FROM/TO constraint.
ERROR:Xst:1489 - Constraint annotation failed.

 

I've attached the complete project also along with this message. The project file is in ...\pulse_mod\pulse_mod_tp   folder named as first.ise. Please help me figure out this problem.

 

 

Milan

 

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ywu
Xilinx Employee
Xilinx Employee
8,495 Views
Registered: ‎11-28-2007

Several problems in your design:

 

* If you are not designing a multi-rate system, keep all sampling periods the same as the simulink system period. Your sysgen designs don't even use clocks, but the sampling periods of sysgen blocks and simulink system period are different, so the tool generates a clock enable. This clock enable doesn't drive anything because there is no synchronous elements in your sysgen design.

 

* Try not to use sysgen blocks (sysgen counters in your example) outside gateway in and gateway out blocks

 

*  Once you fix the problems in your sysgen models and regerate HDL netlists, go back to ISE and change the "Keep Hierarchy" systhesis option to "Yes" (see attached snapshot below).

 

Cheers,
Jim
ScreenHunter_01 Nov. 28 07.22.gif
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maharjanmilan
Participant
Participant
8,479 Views
Registered: ‎07-11-2009

Hi Jim,

           Thanks for your suggestion. Let me tell you what I'm trying to accomplish.

 

 I'm trying to take two 60 hz sinusoidal inputs and substract the 2nd sinusoid from 1st. The difference sinusoid is then compared with a 10 khz triangular waveform to generate a PWM wave at the output. I'm using digilent PmodAD1 12 bit A/D converter to digitize the above sinusids and triangular waveforms. The A/D converter digitizes the signal serially so ser2_p block will convert these serial data into parallel data and these data will be available every 1 us. That's why the gateway in  blocks in sinu_map_cw and tri_map_cw has 1 us sample period. In fact, my specification for clock is,

 

FPGA clock period = 31.25ns

gateway in sample period = 1 us

simulink period =31.25 ns

 with clock enable option

 

 

 Since, I can apply 0-3 V positive signal only as input to A/D converter which is represented as 2^12-1 levels, these 2^12-1 levels are mapped back to 0-3V in file sinu_map,mdl  and +/-1.5V in tri_map.mdl.

 

The reason that I used sysgen blocks (counters) outside the gateway in and gateway outs is to make sure that it's acutally mapping 4095 levels back to 3V and +/- 1.5V respectively. I don't know the consequences of doing that. I'll try by removing these counters as you suggested.

 

About the clock enable,

                                   I'm trying to follow the example given in xilinx DSP documentation, http://www.xilinx.com/support/documentation/sw_manuals/sysgen_user.pdf    page 73.

 

According to this doumentation page, 47" Clock Handling in HDL" , the clock wrapper <design>_cw.vhd will generate the desired clock enable and the "ce" signal that poped up while instantiating the sys gen block is to allow the clock wrapper to be used as black box in system generator designs. That's why, these "ce" signals are assigned as'1' in my design.

 

              Now, can you please suggest me whether I'm in right direction or not? If I'm wrong, can you please correct me. I'm not so sure about this clock wrapper but I tried.

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maharjanmilan
Participant
Participant
8,467 Views
Registered: ‎07-11-2009

Hi Jim,

           I tried to follow your suggestions,

 

1)  keep all sampling periods the same as the simulink system period

2)Try not to use sysgen blocks (sysgen counters in your example) outside gateway in and gateway out blocks

3)Keep "Hierarchy" systhesis option to "Yes"

 

  Still I couldnot synthesize my project. It seems that I'm running into one trouble after another. I generated the HDl netlists with all sampling period as 1 us (same as simulink system period) and created a new ISE project but it gave me the following error when I tried to synthesize,

 

ERROR:Xst:2369 - Empty project file "D:\my_pwm\my_top\my_top.prj"

 

I tried my best but couldnot solve it.  I've attached the whole folder. Pls help me.

 

 

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ywu
Xilinx Employee
Xilinx Employee
8,452 Views
Registered: ‎11-28-2007

Your understanding of how clock enable is handled in sysgen is correct. However, clock enable signals only work if a design has synchronous elements (i.e. logic using clocks). The problem with your sysgen models is that they are purely combinatorial. If you want to get clock enables to work, you would need to add pipeline registers to your models.

 

Regarding the empty project file error, it looks like the project files somehow got corrupted. I would re-build the project from scratch (i.e. delete the sysgen output directoies and regenerate all HDL netlists, switch the libraries in sysgen, and then add .sgp and only .sgp files to your ISE project). In the end, the project window in Proj Nav should look like the picture below.

Cheers,
Jim
ScreenHunter_13 Nov. 29 10.38.gif
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maharjanmilan
Participant
Participant
8,444 Views
Registered: ‎07-11-2009

Hi Jim,

           Thanks a lot for your reply. I'll try again from scratch to solve "Empty project file error". In the mean time can you please tell me how to add pipeline registers to my models to make them synchronous and get clock enable to work? Will this enable me to feed the parallel data from serial_to_p block to the my_sinu_map and my_tri_map block @ 1MHz with FPGA clock of 31.25 ns (32 MHz)?

 

          I just build the blocks and when I simulated them in simulink, it just gave me the desired outputs. That's the reason my design blocks turned out to be all combinatorial. I didn't know, it will be difficult to actually implement it in FPGA board with this approach.

 

 

Milan

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