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Visitor
Visitor
18,231 Views
Registered: ‎08-19-2008

problems division

Hey I have problems with division in VHDL. I have 2 std_logic_vector and would like to creat a third by division!

 

signal u_ist : std_logic_vector (13 downto 0);

signal adj  : std_logic_vector (13 downto 0);

signal answer  : std_logic_vector (13 downto 0);

 

the operation should work like this:

 

u_ist (0-16383 bit) = 0-30volt

adj (0-16383 bit) = 0-10ohm

anwer (0-16383 bit) = 0-10ampere

 

answer = u_ist / adj;

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Historian
Historian
18,212 Views
Registered: ‎02-25-2008


mehnert wrote:

Hey I have problems with division in VHDL. I have 2 std_logic_vector and would like to creat a third by division!

 

signal u_ist : std_logic_vector (13 downto 0);

signal adj  : std_logic_vector (13 downto 0);

signal answer  : std_logic_vector (13 downto 0);

 

the operation should work like this:

 

u_ist (0-16383 bit) = 0-30volt

adj (0-16383 bit) = 0-10ohm

anwer (0-16383 bit) = 0-10ampere

 

answer = u_ist / adj;


Use the numeric_std library's unsigned type. Convert your std_logic_vector to unsigned. do your division, but be aware of binary point issues.

 

-a

----------------------------Yes, I do this for a living.
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Visitor
Visitor
18,195 Views
Registered: ‎08-19-2008

For testbench and syntax this wokrs but not for synthese 

 

signal u_ist : std_logic_vector (13 downto 0) := "01111111111111";
signal adj : std_logic_vector (13 downto 0) := "00111111111111";
signal ergebnis : std_logic_vector (13 downto 0);

signal u_ist_un : unsigned (15 downto 0);
signal adj_un : unsigned (13 downto 0);
signal ergebnis_un : unsigned (15 downto 0);
signal x : unsigned (26 downto 0);

 

 

u_ist_un <= (unsigned (u_ist))*"11";
adj_un <= unsigned (adj);

ergebnis_un <= (u_ist_un/adj_un);
x <= ergebnis_un*"11001100110";
ergebnis <= (std_logic_vector (x (13 downto 0)));

 


ERROR:Xst:769 - "...unsig.vhd" line 50: Operator <INVALID OPERATOR> must have constant operands or first operand must be power of 2

Message Edited by mehnert on 08-20-2008 12:34 AM
Message Edited by mehnert on 08-20-2008 12:34 AM
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Highlighted
Historian
Historian
18,174 Views
Registered: ‎02-25-2008


mehnert wrote:

For testbench and syntax this wokrs but not for synthese 

 

signal u_ist : std_logic_vector (13 downto 0) := "01111111111111";
signal adj : std_logic_vector (13 downto 0) := "00111111111111";
signal ergebnis : std_logic_vector (13 downto 0);

signal u_ist_un : unsigned (15 downto 0);
signal adj_un : unsigned (13 downto 0);
signal ergebnis_un : unsigned (15 downto 0);
signal x : unsigned (26 downto 0);

 

 

u_ist_un <= (unsigned (u_ist))*"11";
adj_un <= unsigned (adj);

ergebnis_un <= (u_ist_un/adj_un);
x <= ergebnis_un*"11001100110";
ergebnis <= (std_logic_vector (x (13 downto 0)));

 


ERROR:Xst:769 - "...unsig.vhd" line 50: Operator <INVALID OPERATOR> must have constant operands or first operand must be power of 2

Message Edited by mehnert on 08-20-2008 12:34 AM
Message Edited by mehnert on 08-20-2008 12:34 AM

 

Whoops, you're right, and page 507 of XST User Guide v10.1 says so.

 

I suppose I thought it would infer one of the FPGA's multipliers.

 

Integer division by factors other than a power-of-two are not supported.

 

Perhaps try using the math_real library. Convert your operands to type real and do the division. This may make your resource usage go sky-high. Good luck.

 

-a

----------------------------Yes, I do this for a living.
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Highlighted
Teacher
Teacher
12,788 Views
Registered: ‎08-14-2007

Hi,

there's a divider IP-core available in coregen. It is highly configurable to your needs.

This is probably the fastest and most compact approach for your application.

 

 

Have a nice synthesis

  Eilert

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