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Adventurer
Adventurer
4,691 Views
Registered: ‎03-31-2017

"Open IP example design" not using the requested HDL?

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I'm generating some Ethernet IP on 2015.4 (10G Ethernet PCS/PMA (10GBASE-R/KR)), on two different computers. The xci requests Verilog output. On one computer, I actually get Verilog output. On the second computer, Vivado generates VHDL output, and modifies my xci to change the requested HDL from Verilog to VHDL.

 

Does anyone have a fix for this? It only happens on the Vivado GUI for "Open IP example design" - running a tcl open_example_project does the right thing.

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Adventurer
Adventurer
8,379 Views
Registered: ‎03-31-2017

Re: "Open IP example design" not using the requested HDL?

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Ok, fixed, I think. The problem happens when you have a project which needs both VHDL and Verilog output.

 

If you use the GUI to 'Open IP example design', then the target language in the xci file (PROJECT_PARAM.PREFHDL) is ignored, and the project's target language is used instead (Tools > Project Settings > Target language). So, you have to set the target language independently in the GUI for each set of example design outputs.

 

However, if you use the tcl flow, open_example_project does correctly read PROJECT_PARAM.PREFHDL from the xci.

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Xilinx Employee
Xilinx Employee
4,686 Views
Registered: ‎08-01-2008

Re: "Open IP example design" not using the requested HDL?

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check the product guide . The reason is only VHDL example design available so even if you are targeting for verilog you will vhdl only . Information provided in product guide
Thanks and Regards
Balkrishan
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Xilinx Employee
Xilinx Employee
4,684 Views
Registered: ‎08-01-2008

Re: "Open IP example design" not using the requested HDL?

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what is the core version and IP name. In case product guide mention both language than core should generate both language example design
Thanks and Regards
Balkrishan
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Moderator
Moderator
4,676 Views
Registered: ‎07-21-2014

Re: "Open IP example design" not using the requested HDL?

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@eml

 

As per my understanding from your post, you are using two separate projects in two separate machines to generate two separate .xci files. One project uses VHDL to deliver IP files and other project uses Verilog?

 

What was the targeted language used under project settings before generating the core?

 

Thanks,
Anusheel
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Adventurer
Adventurer
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Registered: ‎03-31-2017

Re: "Open IP example design" not using the requested HDL?

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Not quite - exactly the same project, being implemented on two different computers. The xci requests Verilog. This works on one computer, producing Verilog, as expected. On the second computer, it actually produces VHDL, and changes the xci to show VHDL instead of Verilog. The only way to get the requested Verilog files on the second computer is to run the tcl directly.

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Moderator
Moderator
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Registered: ‎07-21-2014

Re: "Open IP example design" not using the requested HDL?

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@eml

 

Can you please upload the scripts here for us to understand the flow?

 

Thanks,
Anusheel
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Adventurer
Adventurer
8,380 Views
Registered: ‎03-31-2017

Re: "Open IP example design" not using the requested HDL?

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Ok, fixed, I think. The problem happens when you have a project which needs both VHDL and Verilog output.

 

If you use the GUI to 'Open IP example design', then the target language in the xci file (PROJECT_PARAM.PREFHDL) is ignored, and the project's target language is used instead (Tools > Project Settings > Target language). So, you have to set the target language independently in the GUI for each set of example design outputs.

 

However, if you use the tcl flow, open_example_project does correctly read PROJECT_PARAM.PREFHDL from the xci.

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Adventurer
Adventurer
3,902 Views
Registered: ‎03-31-2017

Re: "Open IP example design" not using the requested HDL?

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However, if you use the tcl flow, open_example_project does correctly read PROJECT_PARAM.PREFHDL from the xci.

 

But read_ip does not. This all needs to be documented somewhere.

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