cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Adventurer
Adventurer
5,105 Views
Registered: ‎03-31-2017

"Open IP example design" not using the requested HDL?

Jump to solution

I'm generating some Ethernet IP on 2015.4 (10G Ethernet PCS/PMA (10GBASE-R/KR)), on two different computers. The xci requests Verilog output. On one computer, I actually get Verilog output. On the second computer, Vivado generates VHDL output, and modifies my xci to change the requested HDL from Verilog to VHDL.

 

Does anyone have a fix for this? It only happens on the Vivado GUI for "Open IP example design" - running a tcl open_example_project does the right thing.

0 Kudos
Reply
1 Solution

Accepted Solutions
Adventurer
Adventurer
8,793 Views
Registered: ‎03-31-2017

Ok, fixed, I think. The problem happens when you have a project which needs both VHDL and Verilog output.

 

If you use the GUI to 'Open IP example design', then the target language in the xci file (PROJECT_PARAM.PREFHDL) is ignored, and the project's target language is used instead (Tools > Project Settings > Target language). So, you have to set the target language independently in the GUI for each set of example design outputs.

 

However, if you use the tcl flow, open_example_project does correctly read PROJECT_PARAM.PREFHDL from the xci.

View solution in original post

0 Kudos
Reply
7 Replies
Xilinx Employee
Xilinx Employee
5,100 Views
Registered: ‎08-01-2008
check the product guide . The reason is only VHDL example design available so even if you are targeting for verilog you will vhdl only . Information provided in product guide
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Reply
Xilinx Employee
Xilinx Employee
5,098 Views
Registered: ‎08-01-2008
what is the core version and IP name. In case product guide mention both language than core should generate both language example design
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
0 Kudos
Reply
Moderator
Moderator
5,090 Views
Registered: ‎07-21-2014

@eml

 

As per my understanding from your post, you are using two separate projects in two separate machines to generate two separate .xci files. One project uses VHDL to deliver IP files and other project uses Verilog?

 

What was the targeted language used under project settings before generating the core?

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

0 Kudos
Reply
Adventurer
Adventurer
5,071 Views
Registered: ‎03-31-2017

Not quite - exactly the same project, being implemented on two different computers. The xci requests Verilog. This works on one computer, producing Verilog, as expected. On the second computer, it actually produces VHDL, and changes the xci to show VHDL instead of Verilog. The only way to get the requested Verilog files on the second computer is to run the tcl directly.

0 Kudos
Reply
Moderator
Moderator
5,005 Views
Registered: ‎07-21-2014

@eml

 

Can you please upload the scripts here for us to understand the flow?

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

0 Kudos
Reply
Adventurer
Adventurer
8,794 Views
Registered: ‎03-31-2017

Ok, fixed, I think. The problem happens when you have a project which needs both VHDL and Verilog output.

 

If you use the GUI to 'Open IP example design', then the target language in the xci file (PROJECT_PARAM.PREFHDL) is ignored, and the project's target language is used instead (Tools > Project Settings > Target language). So, you have to set the target language independently in the GUI for each set of example design outputs.

 

However, if you use the tcl flow, open_example_project does correctly read PROJECT_PARAM.PREFHDL from the xci.

View solution in original post

0 Kudos
Reply
Adventurer
Adventurer
4,316 Views
Registered: ‎03-31-2017

However, if you use the tcl flow, open_example_project does correctly read PROJECT_PARAM.PREFHDL from the xci.

 

But read_ip does not. This all needs to be documented somewhere.

0 Kudos
Reply