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6,505 Views
Registered: ‎01-12-2017

"WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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With Vivado 2016.2, I'm getting the "expecting unsigned expression" warning on the statements below with negative values, but not on the statements with positive values. This makes no sense. Can someone please explain why? Is this a Vivado bug?

 

   constant A1   : signed(14 downto 0) := to_signed( -33,15);
   constant A2   : signed(14 downto 0) := to_signed(-279,15);
   constant A3   : signed(14 downto 0) := to_signed(-322,15);

   constant B1   : signed(14 downto 0) := to_signed( 417,15);
   constant B2   : signed(14 downto 0) := to_signed(1922,15);
   constant B3   : signed(14 downto 0) := to_signed(3193,15);
Jeff
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Registered: ‎07-21-2014

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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@jeffreybmeyers@brimdavis

 

I have filed a CR# 976893 for incorrect to_signed warnings issue and CR# 976894 for showing incorrect red-lines on valid RTL.

 

Thanks,
Anusheel
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14 Replies
Moderator
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Registered: ‎11-09-2015

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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Hi @jeffreybmeyers,

 

Can you share a test case I can use to try to reproduce your issue?

 

I have tried in 2016.2 with the file attached and I am not seeing the warning.

 

Thanks and Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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6,466 Views
Registered: ‎01-12-2017

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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Florent,

 

Thanks for looking at this and providing a test case with the info I provided. In trying to create my own test case, I've failed to get the warning message in the limited environments of the test cases I've created. The example that I posted is just one instance of these warnings appearing in a very complex system, and I would have to spend a great deal of time ferreting out how to replicate the scenario in such a complex environment. So, I guess I'll have to just let it go for now. I can only assume that the tool goes ahead and uses the value provided, since it's just citing it as a warning.

 

Thanks for your help.

Jeff
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6,465 Views
Registered: ‎01-12-2017

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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...Just an added note: The warnings are consistent in every case with negative integers in a "to_signed" function, and no warning is created for positive integers, as I indicated in the original post. It's also interesting to me that the warning references "unsigned" and not "signed", even though it's a signed expression and not an unsigned one.

 

BTW, I am aware of the issue with the length value provided to the function needing to be of type natural, and not integer. I see those warnings showing up when <signal>'length is used as the length value. Unfortunately, trying to cast the value as natural, i.e. "natural(<signal>'length)," has no effect on the warning. It would seem that if VHDL assigned the 'length attribute to be of type "natural," that would be helpful, as this value can never be negative anyway, and that would resolve that little issue.

 

Jeff
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Registered: ‎07-21-2014

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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@jeffreybmeyers

 

One quick question, are you getting this warning only with VHDL-2008? 

Can you set the RTL type to VHDL and let me know, I am seeing similar warning at my end with 2008. I will update this thread with more findings.

 

Thanks,
Anusheel
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Registered: ‎01-12-2017

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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@anusheel

 

I changed the VHDL 2008 property to VHDL on one of the files that was generating the warning messages, but still got the warnings.

Jeff
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Observer david.bleakley
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Registered: ‎10-27-2008

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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I get this warning too, only on the negative  post_add value of the record on 2016.2:

 

    constant C_CSC_CHANNEL_DEFAULT_YG : wave_csc_channel_control_t := (
      pre_yg        => to_signed(0,18),
      pre_b         => to_signed(0,18),
      pre_r         => to_signed(0,18),
      yg_coef       => to_signed(32768,18),
      b_coef        => to_signed(0,18),
      r_coef        => to_signed(0,18),
      post_add      => to_signed(-2048,18),
      limit_enabled => '1',
      alpha_enabled    => '0'
    );
6,231 Views
Registered: ‎01-12-2017

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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@david.bleakley

 

Yes, that is exactly the same thing that I'm seeing. Only the negative values being assigned get the warning.

 

I was not able to create a code snippet that generates the same warning. I'm wondering if you might be able to. The snippet that @florentw created didn't generate the warning, and I couldn't figure out how to create something that would do it either, without spending more time than I had available.

Jeff
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Observer david.bleakley
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Registered: ‎10-27-2008

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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I have limited time too and I would not be able to post my current design.

I may be able to make a design if I can find a moment, but I am not sure how soon.

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Observer rmm92vt
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Registered: ‎02-20-2014

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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I think this is a problem with how Vivado 2016.2 is handling the ieee.math_real package. Is the OP using it in his code by any chance?

 

For years, I've been using math_real with Xilinx tools to help create scaling constants that don't have to be recomputed every time I change a generic dictating the data width. With the more recent versions of Vivado, I'm now seeing some weirdness with math_real. The attached foo.vhd shows a typical application.

 

If you create a new project in 2016.2 with this as the top-level, you will get red-squigglies in the editor indicating problems on lines 15, 31 & 32 as follows:

 

15: Cannot find <math_real> in library <ieee>

31: <math_pi> is not declared

32: <math_pi> is not declared

 

However, if you run synthesis & implementation, everything turns out fine with no warnings... other than some polite reminders to create timing constraints.

 

Being a worry-wart, I wanted to get rid of those red-squigglies. I noticed in the Xilinx install that the math_real package is found at <install_dir>/data/vhdl/src/ieee_2008/math_real.vhdl

 

For some reason you can no longer set the VHDL 2008 checkbox under Project Settings (it's gone). But you CAN select VHDL 2008 as the "Type" for individual source files by right-clicking in hierarchy and selecting "Source Node Properties" then hit the "..." next to "Type:  VHDL" and change it to "VHDL 2008"

 

The red squigglies are now gone. BUT, if you rebuild, you'll now see that you have the previously mentioned "expecting unsigned expression" warnings for to_signed(N,W) operations when N is negative. This happens on lines 32 & 34.

 

Go figure. So there's your test case. Let us know what's going on with math_real. How are we supposed to be using it these days?

 

Thanks,

Bob

 

---------------------------------------------------------------------------
-- Test case for suspect Vivado 2016.2 behavior related to the
-- numeric_std and math_real packages:
-- * When File Type = "VHDL": editor complains it cannot find the
--   math_real package
-- * When File Type = "VHDL 2008": synthesis reports
--   "[Synth 8-5827] expecting unsigned expression..."
--   for to_signed(N,W) when N is a negative integer
-- Design builds fine in both cases
---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity foo is
generic (
   DW  : positive := 16);
    
port (
   CLK : in std_logic;
   SEL : in std_logic_vector(2 downto 0);
   A   : in std_logic_vector(DW-1 downto 0);
   B   : in std_logic_vector(DW-1 downto 0);
   Y   : out std_logic_vector(DW-1 downto 0));
end foo;

architecture behavior of foo is
   
   constant PI     : signed(DW-1 downto 0) := to_signed(integer(2.0**12*(MATH_PI)),DW);  -- No warning
   constant NEG_PI : signed(DW-1 downto 0) := to_signed(integer(2.0**12*(-MATH_PI)),DW); -- [Synth 8-5827] expecting unsigned expression
   constant C      : signed(DW-1 downto 0) := to_signed(123,16);  -- No warning
   constant D      : signed(DW-1 downto 0) := to_signed(-123,16); -- [Synth 8-5827] expecting unsigned expression

   signal mult1    : std_logic_vector(2*DW-1 downto 0);
   signal mult2    : std_logic_vector(2*DW-1 downto 0);
   signal e        : std_logic_vector(DW-1 downto 0);
   signal f        : std_logic_vector(DW-1 downto 0);

begin

   mult1 <= std_logic_vector( signed(A) * PI );
   mult2 <= std_logic_vector( signed(A) * NEG_PI );
   e <= mult1(30 downto 15);
   f <= mult2(30 downto 15);

   process(CLK)
   begin
      if rising_edge(CLK) then
         case (SEL) is
            when "000"  => Y <= A;
            when "001"  => Y <= B;
            when "010"  => Y <= std_logic_vector(C);
            when "011"  => Y <= std_logic_vector(D);
            when "100"  => Y <= e;
            when others => Y <= f;
         end case;
      end if;
   end process;
   
end behavior;

 

3,660 Views
Registered: ‎01-12-2017

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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Jeff
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Registered: ‎11-09-2015

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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Hi @jeffreybmeyers,

 

I can reproduce your issue. I don't really know why there is this issue.

 

My main suggestion is to move to a more recent version of vivado (there have been improvemenents for VHDL2008).

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Scholar brimdavis
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Registered: ‎04-26-2012

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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@rmm92vt "you will get red-squigglies in the editor indicating problems <snip> However, if you run synthesis & implementation, everything turns out fine with no warning"

 

I've also seen a number of cases where the on-line editor syntax check flags legal VHDL that the synthesizer doesn't warn/error about, e.g.:

  https://forums.xilinx.com/t5/Synthesis/Cannot-find-fixed-pkg-in-IEEE-or-IEEE-PROPOSED/m-p/718690#M19239

  https://forums.xilinx.com/t5/Synthesis/ieee-math-real-support-with-Vivado/m-p/749313#M20754

 

It appeared to me that the editor's online syntax checker is using a different parser and/or libraries than the synthesizer proper, but I haven't checked this in 2017.1 yet.

 

----------------------

Xilinx has also fouled up VHDL libraries in a number of other ways, e.g.:

 

Xilinx uses VHDL-2008 libraries when simulating VHDL-93 code, breaking existing code:

  https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-2016-3-Simulator-uses-VHDL-2008-IEEE-library-for-VHDL/m-p/733474/highlight/true#M17238

 

Xilinx's "support" for VHDL fixed point is an ugly hack, non-compliant with the LRM:

  https://forums.xilinx.com/t5/Synthesis/VIVADO-2016-3-float-pkg-is-not-correctly-compiled-in-ieee/m-p/730379#M19832

  https://forums.xilinx.com/t5/Synthesis/Library-2008-does-is-it-work-under-Vivado-2016-4/m-p/759279#M21208

 

And a few more that I can't find the threads for just now.

 

-Brian

 

 

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Registered: ‎07-21-2014

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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@jeffreybmeyers@brimdavis

 

I don't see any warnings in the latest version of Vivado when the file is compiled as VHDL instead of VHDL-2008. However, the warnings are not correct and I will file a CR for this issue. Sharing a CR number in few hours.

 

Also, I do see a red-line when VHDL2008 is not set. Let me check this issue also, I will keep you posted.

 

Thanks,
Anusheel
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7,331 Views
Registered: ‎07-21-2014

Re: "WARNING: [Synth 8-5827] expecting unsigned expression" on to_signed function

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@jeffreybmeyers@brimdavis

 

I have filed a CR# 976893 for incorrect to_signed warnings issue and CR# 976894 for showing incorrect red-lines on valid RTL.

 

Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
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Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
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