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Explorer
Explorer
7,131 Views
Registered: ‎04-28-2010

real data types for a port

 

hello,

        Can I not declare a port as real data type in the entity declaration of the code snippet below? I am getting error while trying to synthesize my design. Pls help.

The error says: Signal <a> of type real is not supported

 

 

entity twoD_array_opr is
Port ( a : in real;
b : in real;
clk:in std_logic;
c : out real);
end twoD_array_opr;

Best Regards
Chandrajit
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Xilinx Employee
Xilinx Employee
7,096 Views
Registered: ‎08-01-2008

you need to include correct library

use IEEE.MATH_REAL.ALL;

this third party blog may helpful
http://vhdlguru.blogspot.in/2011/06/using-real-data-types-in-vhdl.html
Thanks and Regards
Balkrishan
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Explorer
Explorer
7,080 Views
Registered: ‎04-28-2010

Yes I have used the use IEEE.MATH_REAL.ALL; library..but still the error is coming up.

Best Regards
Chandrajit
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Explorer
Explorer
6,802 Views
Registered: ‎04-28-2010

Real data types are not synthesis-able..I solved my problem..thanks...

Best Regards
Chandrajit
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