06-24-2016 02:02 AM
Hello, I've tried retiming in Vivado 2016 and found that it seems doesn't work at all =/
Here's simple example
module mult #( parameter BW = 32 )( input clk , input [BW-1:0] a , input [BW-1:0] b , output [2*BW-1:0] rez ); wire [2*BW-1:0] w_prod; reg [2*BW-1:0] rez0; reg [2*BW-1:0] rez1; reg [2*BW-1:0] rez2; reg [2*BW-1:0] rez3; reg [2*BW-1:0] rez4; assign w_prod = a*b; always @(posedge clk) begin rez0 <= w_prod; rez1 <= rez0; rez2 <= rez1; rez3 <= rez2; rez4 <= rez3; end assign rez = rez4; endmodule
I see the same structure after synthesis - 4 one to another connected DSP units with no register between them. No matter if I set -retiming true or not. And the same timings result.
So how to enable retiming and resource sharing in Vivado 2016?
06-24-2016 02:34 AM
With retiming option enabled in Vivado synthesis. I see the following INFO message in the log file.
INFO: [Synth 8-5816] Retiming module `mult`
Effective logic levels is 0, the effective logic levels of whole design is 0
Skipping retiming for this module
INFO: [Synth 8-5816] Retiming module `mult' done
FYI: Logic levels means the levels of combinational logic between two timing end points. E.g. a LUT is one level of logic. If there are 3 LUTs between two FFs, we say there are three logic levels.
06-28-2016 08:00 AM
I've provided 4 D-triggers after long combination logic, enabled Retiming on synthesis and Retiming on Place&Route
So know I see 7Level logic (which occures timing violation) and this 7level logic connected to SRL shifter. So Vivado didn't use it for retiming.
Seems that retiming doesn't work in Vivado and thats the reason why Xilinx keep silience about this feature.
06-28-2016 03:18 PM
Can you please share the new test case?