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6,413 Views
Registered: ‎12-04-2013

sequential type is unconnected in block <fpga_top>

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 in simulation everything is working fine. but in synthesis output is not proper 

these i connected to other modules also 

can u plase help me  ASAP

 

module control_block (clk,reset,rx_empty,rx_data,data,tx_enable,ex_i_apb_AHB_Slave_dma_haddr,ex_i_apb_AHB_Slave_dma_hwrite,ex_i_apb_AHB_Slave_dma_hready,ex_i_apb_AHB_Slave_dma_hsel,ex_i_apb_AHB_Slave_dma_htrans,ex_i_apb_AHB_Slave_dma_hsize,ex_i_apb_AHB_Slave_dma_hwdata,tx_data);

input clk,reset,rx_empty,tx_enable;
input [7:0] rx_data,data;
output reg [31:0] ex_i_apb_AHB_Slave_dma_haddr,ex_i_apb_AHB_Slave_dma_hwdata;
output reg ex_i_apb_AHB_Slave_dma_hwrite,ex_i_apb_AHB_Slave_dma_hready,ex_i_apb_AHB_Slave_dma_hsel;
output reg [1:0] ex_i_apb_AHB_Slave_dma_htrans;
output reg [2:0] ex_i_apb_AHB_Slave_dma_hsize;
output reg [7:0] tx_data;

parameter [3:0] idle = 4'b0000;
parameter [3:0] s1 = 4'b0001;
parameter [3:0] s2 = 4'b0010;
parameter [3:0] s3 = 4'b0011;
parameter [3:0] s4 = 4'b0100;
parameter [3:0] s5 = 4'b0101;
parameter [3:0] s6 = 4'b0110;
parameter [3:0] s7 = 4'b0111;
parameter [3:0] s8 = 4'b1000;
parameter [3:0] s9 = 4'b1001;
parameter [3:0] s10 = 4'b1010;
parameter [3:0] s11 = 4'b1011;

reg addr_ready,wdata_ready,p1;
reg [3:0] present_state,next_state;
reg enable_newdata,variable_newdata;
reg [31:0] haddr_q;

always @ (posedge clk or posedge reset)
begin
if(reset) begin
haddr_q <= 32'b0;
end
else begin
haddr_q <= ex_i_apb_AHB_Slave_dma_haddr;
end
end

 

always @ (posedge clk or posedge reset)
begin
if(reset)
begin
present_state<= idle;
end
else
begin
present_state<=next_state;
end
end

 

always @(rx_empty or data or rx_data or haddr_q or present_state or tx_enable or enable_newdata)
//always @ (*)
begin
//default values
next_state = present_state;
next_state = idle;
ex_i_apb_AHB_Slave_dma_hready = 1'b1;
ex_i_apb_AHB_Slave_dma_hsel = 1'b0;
ex_i_apb_AHB_Slave_dma_htrans = 2'b00;
ex_i_apb_AHB_Slave_dma_hwdata = 32'b0;
ex_i_apb_AHB_Slave_dma_haddr = 32'b0;
ex_i_apb_AHB_Slave_dma_hwrite = 1'b0;
tx_data = 8'b0;
ex_i_apb_AHB_Slave_dma_hsize = 3'b010;
//ex_i_apb_AHB_Slave_dma_hsize = 2'b11;

case(present_state)

idle : if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr = 32'b0;
next_state = s1;

end
else begin
next_state = idle;
ex_i_apb_AHB_Slave_dma_haddr = 32'b0;
end

// load the adrress

s1:if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr[7:0] = rx_data;
next_state = s2;
// ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
ex_i_apb_AHB_Slave_dma_haddr [31:8] =24'b0;
end
else begin
next_state = s1;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end
s2: if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr[15:8] = rx_data;
next_state = s3;
ex_i_apb_AHB_Slave_dma_haddr[7:0] = ex_i_apb_AHB_Slave_dma_haddr[7:0];
ex_i_apb_AHB_Slave_dma_haddr[31:16] = 16'b0;
end
else begin
next_state = s2;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end

s3: if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr[23:16] = rx_data;
next_state = s4;
ex_i_apb_AHB_Slave_dma_haddr[15:0] = ex_i_apb_AHB_Slave_dma_haddr [15:0];
ex_i_apb_AHB_Slave_dma_haddr[31:24] = 8'b0;
end
else begin
next_state = s3;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end

s4: if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr[31:24] = rx_data;
next_state = s5;
ex_i_apb_AHB_Slave_dma_haddr[23:0] = ex_i_apb_AHB_Slave_dma_haddr[23:0];
end
else begin
next_state = s4;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end
// load the command

s5: if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
next_state = s6;
ex_i_apb_AHB_Slave_dma_hwrite = rx_data[7];
ex_i_apb_AHB_Slave_dma_hready =rx_data[6];
ex_i_apb_AHB_Slave_dma_hsel = rx_data[5];
ex_i_apb_AHB_Slave_dma_htrans = rx_data[4:3];
ex_i_apb_AHB_Slave_dma_hsize = rx_data[2:0];
end
else begin
next_state = s5;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end

s6: if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
if(ex_i_apb_AHB_Slave_dma_hwrite)
begin
next_state = s7;
end
else next_state = s11;
end
else begin
next_state = s6;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end

//load write data to AHB slave port

s7: if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_hwdata[7:0] = rx_data;
next_state = s8;
ex_i_apb_AHB_Slave_dma_hsel = 1'b0;
ex_i_apb_AHB_Slave_dma_htrans = 2'b00;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;

end
else begin
next_state = s7;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end

s8: if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
ex_i_apb_AHB_Slave_dma_hwdata[15:8] = rx_data;
next_state = s9;

end
else begin
next_state = s8;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end
s9: if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
ex_i_apb_AHB_Slave_dma_hwdata[23:16] = rx_data;
next_state = s8;

end
else begin
next_state = s9;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end

s10: if(rx_empty==1'b0)
begin
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
ex_i_apb_AHB_Slave_dma_hwdata[31:24] = rx_data;
next_state = idle;

end
else begin
next_state = s10;
ex_i_apb_AHB_Slave_dma_haddr = haddr_q;
end

//read data from AHB slave port

s11: begin
ex_i_apb_AHB_Slave_dma_hsel = 1'b0;
ex_i_apb_AHB_Slave_dma_htrans = 2'b00;
ex_i_apb_AHB_Slave_dma_hready = 1'b0;
//next_state = s11;
wdata_ready =1'b0;
// end

if((tx_enable==1'b1)&&(enable_newdata==1'b1))
begin
tx_data = data;
next_state = s11;
end

//else if (!tx_enable) begin
/// next_state = idle;
//end
// end
else next_state = s11;
end
default :begin
next_state = idle;
ex_i_apb_AHB_Slave_dma_haddr = 32'b0;
end
endcase

end
//end

//initial begin
// enable_newdata <= 1'b0;
// variable_newdata <= 1'b1;
// end

always @ (data or variable_newdata)
begin
if(variable_newdata>0)
begin
enable_newdata <= 1'b0;
variable_newdata <= variable_newdata-1'b1;
end
else begin
enable_newdata <= 1'b1;
variable_newdata <= 1'b0;
end
end

endmodule

 

 

 

 

warnings?

 

 

 

WARNING:Xst:2677 - Node <control_bank/haddr_q_31> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_30> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_29> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_28> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_27> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_26> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_25> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_23> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_22> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_21> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_20> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_19> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_18> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_17> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_15> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_14> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_13> of sequential type is unconnected in block <top_apb_fabric>.

 

WARNING:Xst:2677 - Node <control_bank/haddr_q_11> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_10> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_9> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_8> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_7> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_6> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_5> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_4> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_3> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_2> of sequential type is unconnected in block <top_apb_fabric>.
WARNING:Xst:2677 - Node <control_bank/haddr_q_1> of sequential type is unconnected in block <top_apb_fabric>.

 

 

same error for all bis of ex_i_apb_AHB_Slave_dma_hwdata && ex_i_apb_AHB_Slave_dma_haddr 

 

 

 

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1 Solution

Accepted Solutions
Highlighted
8,291 Views
Registered: ‎12-04-2013

Re: sequential type is unconnected in block <fpga_top>

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i simulated as it is. working fine in simulation, but not working on FPGA.

 second point u ask me change  ex_i_apb_AHB_Slave_dma_haddr as wire . but i need to use this signal in always block thats why i kept as reg.

 

why we will get these kind of warnings???/

View solution in original post

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5 Replies
6,404 Views
Registered: ‎12-04-2013

Re: sequential type is unconnected in block <fpga_top>

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even i saw in in view RTL schematic  . there all pins are connected properly

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Teacher muzaffer
Teacher
6,401 Views
Registered: ‎03-31-2012

Re: sequential type is unconnected in block <fpga_top>

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Do you simulate your design ? Does it do what you want it to do? If it simulates properly don't worry about these optimization warnings. If it doesn't, change your RTL so that your design works OK.

One comment about the design is the output ex_i_apb_AHB_Slave_dma_haddr is not registered. The registered version is haddr_q but this ex_i_apb_AHB_Slave_dma_haddr signal is the output of the module. This is not going to work too well.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Highlighted
8,292 Views
Registered: ‎12-04-2013

Re: sequential type is unconnected in block <fpga_top>

Jump to solution

i simulated as it is. working fine in simulation, but not working on FPGA.

 second point u ask me change  ex_i_apb_AHB_Slave_dma_haddr as wire . but i need to use this signal in always block thats why i kept as reg.

 

why we will get these kind of warnings???/

View solution in original post

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Teacher muzaffer
Teacher
6,391 Views
Registered: ‎03-31-2012

Re: sequential type is unconnected in block <fpga_top>

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I don't know why you checked as accepted. Is your problem solved?
I suggested that you make the haddr_q signal should be the output because that is the register. the other register is the combinational output of the state machine which will have much worse timing.
When you did p&r, did you check timing ? Does it pass timing ?
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
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Historian
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Registered: ‎02-25-2008

Re: sequential type is unconnected in block <fpga_top>

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@vinodhcherukuri1990@gmail.com wrote:

i simulated as it is. working fine in simulation, but not working on FPGA.


Does your simulation include real data/control sources and sinks, or are you just "bit-banging" the various inputs? Because the latter is NOT a simulation. Your simulation hasn't proven anything.


second point u ask me change ex_i_apb_AHB_Slave_dma_haddr as wire . but i need to use this signal in always block thats why i kept as reg.

why we will get these kind of warnings???/


Your code is poorly formatted and totally undocumented. Perhaps reformatting it, and using the Verilog-2001-style module port declarations will help us to understand it. Because all I see is a bunch of obfuscated letters and numbers.

 

Also, you're using a two-process state machine. That's wrong.

----------------------------Yes, I do this for a living.
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