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Registered: ‎05-21-2015

set a SetRelease block from a falling edge of a clock, and or external io signal.

Ok so I have 3 input pins,

Phi2 <- which is a clock signal

IO1 <- which is a io line that is going to be low for at least 450ns

Arm_Request_recieved <- which can be low for at least 44ns

and 1 output pin

arm_request <- which needs to be high until the other unit detects it and then sends back the arm_request_recieved signal

the way I need it to work is, if Phi2 = 1 and IO1 falls, then a SR FF is "set", the out of this is connected to the arm_request pin, once the ARM gets the signal, it will then fire the Arm_Request_recieved line which in turn "resets" the SR.


The SR is as follows


entity SR is
port ( set,reset : in std_logic;
     state : out std_logic );
end SR

architecture behavioural of SR is
signal notQ : std_logic := '0';
signal q2 : std_logic := '0';
   state <= q2;
   q2 <= reset nor notQ;
   notQ <= set nor q2;
end behavioural;



In another component I have my "controller"

Where I want to do logic like this


IF falling_edge(IO1) and Phi2 = '0' then SR_set = '1'


writing it as

if falling_edge(IO1) and Phi2 = '1' then SR_set  <= ‘1’

results it the component being removed and all the lines it is connected being left unconnected. Makes sense as there is nothing to ever set it back to 0 I guess... but should still cover the 1 shot case right?

So I tried

if falling_edge(IO1) and Phi2 = '1' then SR_set  <= ‘1’

else SR_set <= '0'

This is un-synthesisable

if falling_edge(IO1) and Phi2 = '1' then SR_set  <= ‘1’

elsif Phi2 = ‘0’ then SR_set <= '0'

Also un-synthesisable

So I tried

if falling_edge(IO1) and Phi2 = '1' then SR_set  <= ‘1’,’0’ after 30ns

This synthesises fine, no warnings, no errors just seems to be completely ignored and the pins/connections in the schematic are just left unconnected.

What is the best/only way to achieve this?

This is on a 10ns VHDL.

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