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Explorer
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Registered: ‎12-05-2016

'set_property' expects at least one object

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 am trying to create a project in vivado 2017.1 using the sources supplied by a second person. but when i synthesized the project I am getting the following error..

 

[Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

 

its looks like problem in xdc file, but it is not pointing to any line in xdc file. please help.

 

thanks in advance,

 

regards,

Reshma 

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Scholar
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Registered: ‎03-22-2016

Re: 'set_property' expects at least one object

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@reshmaakhil Exactly what it is said - set_property is being passed a null reference.

The command that precedes this one is failing to find the object (by name?).

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Scholar
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Registered: ‎03-22-2016

Re: 'set_property' expects at least one object

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@reshmaakhil Exactly what it is said - set_property is being passed a null reference.

The command that precedes this one is failing to find the object (by name?).

vitorian.com --- We do this for fun. Always give kudos. Accept as solution if your question was answered.
I will not answer to personal messages - use the forums instead.

View solution in original post

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Guide
Guide
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Registered: ‎01-23-2009

Re: 'set_property' expects at least one object

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It is odd that the error message does not give you an XDC file name and a line number...

 

But even without this you can figure out where the problem is - find the error message in the log file (not the errors tab) - from looking at what was going on before the error message you should be able to figure out where the error was generated.

 

Normally, the tool reports the filename and line number. However, I suspect (but don't know for sure) that if the offending Tcl command is in an un-managed constraint file (either a .tcl file added to the project or a file that was read using "source" rather than read_xdc, or even read via read_xdc -unmanaged) then the tools may not report the location of the error.

 

Avrum

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Registered: ‎12-05-2016

Re: 'set_property' expects at least one object

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hi @hbucher,

 

you were correct. some files was missing. so I  created a new project and added all files, now its successfully synthesized .

 

thank you.

regards,

reshma

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Registered: ‎08-08-2018

Re: 'set_property' expects at least one object

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I am getting the same error. 

This is from the hdmi example design.

If I use the out of the box example it goes through synthesis but when I target a new device VU440 I get this error.

I thought it was the .xdc files too but removed all three .xdc files and still getting the same error.

 

Help!  It's eating into my Friday night :-(.

Thanks

 

Screen Shot 2018-08-24 at 9.41.41 PM.png
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Registered: ‎11-04-2010

Re: 'set_property' expects at least one object

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Hi, @dtokhi ,

Please create a new thread for the new question. If necessary, you can add the link of the original post.
Attaching a new question to a thread that has been marked as answered will have less a chance of being found.
Thank you for your cooperation and understanding.

 

PS: Please show the Vivado version you are using in your new post.

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Registered: ‎06-18-2018

Re: 'set_property' expects at least one object

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Unfortunately there are some mistakes in newer version of Vivado. For example I used Vivado 2014.1 to run the Digilent ZYBO base design. It was ok but I have received this error in Vivado 2018.2 for the same projects. I could solve it. It was somewhat crazy!!! For example the ZYBO project has a port called BTNs_4Bits_tri_i but in the xdc it was btns_4Bits_tri_i. The only difference was capital letters. I am so excited why the newer version of Vivado has such a crazy problem but I hope Xilinx will try to modify such error/warnings.

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Guide
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Registered: ‎01-23-2009

Re: 'set_property' expects at least one object

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This is not a "Vivado" problem - this is a problem with the source.

The Vivado design suite database is case sensitive - the command [get_ports BTNs_4Bits_tri_i] is looking for a port object with that exact name - including case. The XDC was using a different name, hence it didn't match. This is the "correct" behavior of XDC.

The problem really stems from VHDL. Most other tools and languages are case sensitive when it comes to user identifiers, but VHDL is not. This leads to a problem - XDC is case sensitive, but VHDL is not.

Xilinx has struggled with this, and, in the past, experimented with special rules for VHDL, and tried to make XDC searches non-case sensitive when the source was VHDL, but remain case sensitive when the source was Verilog/SystemVerilog/EDIF/... This behavior may have changed from version to version.

Since I don't use VHDL, I don't know how the tool currently deals with this, but I suspect (without being sure) that if you ensure that your XDC case is consistent with the case of the identifier in the entity declaration, you won't have a problem.

But, again, this isn't something that you should expect Xilinx to fix.

Avrum

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Registered: ‎06-18-2018

Re: 'set_property' expects at least one object

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Thank you for your response.

But my experience is different. I have used Vivado 2014.1 to synthesis the ZYBO base design. It was run without any problem. Again, I used the Vivado 2018.2 to synthesis the design and it gets errors. The same design with the same files and strategies but different results appeared. So I strongly figure out a Xilinx related issue. It was different for two generations of Vivado. I know that Verilog is Case-Sensitive but VHDL is not. How will you interpret the behaviour of two Vivados? It does not arise from VHDL/Verilog mismatch with XDC. It is a real Xilinx issue.

Thank you for your nice comments.

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Registered: ‎11-13-2015

Re: 'set_property' expects at least one object

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Hi,

I am trying to get a block ram IP out of the Block Memory Generator 8.4 and the OOC run for the configured core fails with the same Error as described by OP.
This happens with Vivado 2018.3

Vivado 2017.4: same project, same Block Memory Generator 8.4, OOC synthesis succeeds.

Why the f is my University paying thousands of euros for software, which fails to build its integrated IP cores?
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Registered: ‎07-23-2019

Re: 'set_property' expects at least one object

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Cause of issue: The issue is due to missing source file(in my case it was an IP that was missing).

Fix: Direct addition of the source file(.xcix) may not work. Remove the file and re-adding the same file worked for me. Sometimes this fix may not work because the missing file will be pointing to some other location or even if the tool is pointing to the correct location vivado may fail to read it, in that case close the project and re-open the same project and then add the missing file, it will clear your issues. No need to create a fresh project for this issue.

 

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Explorer
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Registered: ‎08-02-2019

Re: 'set_property' expects at least one object

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Hello @prajwal-k ,

Your solution did not work work me.

I mean, Closing project, reopen it and create object again.

I m using Vivado 2018.2. I changed FPGA partnumber , then deleted all the things and create only ZYNQ processor7 and ILA and it does not work.

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Registered: ‎09-09-2019

Re: 'set_property' expects at least one object

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[Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

 

That's the error I cannot solve. Please help.

Someone can suggest a workaround?

 

many thanks

Pier

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-14-2008

Re: 'set_property' expects at least one object

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@pierfrancesco.santi Please start a new post for your question, and provide more information. Like what line in which file caused the error. The error message is expected to have the file name and line number.

-vivian

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