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Visitor pudzilla
Visitor
1,538 Views
Registered: ‎03-19-2015

set_property verilog_define for each verilog file

Hi,

 

I've got several verilog files and I need to use different verilog_define for each file. How can I do that?

 

I can only set global define in project mode by command:

set_property verilog_define {ored} [current_fileset]

Is there any way to set unique set of defines for each verilog file? Maybe in tcl script (passing by -source switch) or something simillar to xdc file?

Thanks for your help,

John

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2 Replies
Historian
Historian
1,513 Views
Registered: ‎01-23-2009

Re: set_property verilog_define for each verilog file

I am fairly sure the answer to that is "no".

 

A `define is a verilog macro, and it is tied to the fact that Verilog was (once) an interpreted language. Verilog macros were part of the parsing phase of the Verilog flow; once a `define was defined, it became part of the parsing phase for all the Verilog code that was parsed after the definition. The concept of separate files (and any idea that files were related in any way to namespace or scope) didn't exist in the original Verilog language.

 

So the only way of setting a `define in any other way than in the code being parsed was to set it on the command line, which effectively had it set before the parsing phase began.

 

So, I suspect that what you are trying to do isn't possible. You will probably have to find a different way of doing what you are trying to do.

 

In general (and I don't know if/how this applies to what you are trying to do), `defines are overused. Most of what people do with `defines should really be done with parameters. Parameters have the advantage of being scoped (they are part of the Verilog hierarchy), and being able to be set when a module is instantiated - this make reuse of a module very easy since the customization is done at the instantiation level.

 

So maybe if you explain what you are trying to do we can suggest a way of doing it without the need to override macros on a per-file basis.

 

Avrum

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Visitor pudzilla
Visitor
1,471 Views
Registered: ‎03-19-2015

Re: set_property verilog_define for each verilog file

Thanks for your answer - it's like I thought. I'll have to rewrite my project then.

 

One more question, why SYNTHESIS define is use in Vivado as default? Where I can find information about this in documentation? Are there any more default defines used by synthesis tool?

 

Thanks,

John

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