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Visitor
Visitor
361 Views
Registered: ‎05-22-2020

signal can't be synthesized

Hi everyone, I got some troubles with some signals that cannot be synthesized, does somebody have an idea?

 

Thanks in advance,

regards

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6 Replies
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351 Views
Registered: ‎06-21-2017

Re: signal can't be synthesized

I think the problem is in the while loop.  I don't think it is synthesizable.  This looks like a software construct.  What hardware could the synthesizer build to achieve this loop?

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Scholar
Scholar
348 Views
Registered: ‎08-07-2014

Re: signal can't be synthesized

@S_SUPAERO_FR,

MY recommended style is the 'one process' style (there are many online articles argumentation on the adv/disadv between 1 and 2 process styles. I don't want to debate on them again here).

Simply follow this document - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

Read Chapt 4, "FSM Components", and follow that coding style for correct synthesis results.

 

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Visitor
Visitor
337 Views
Registered: ‎05-22-2020

Re: signal can't be synthesized

Hi bruce_karaffa, thanks you for your response, I removed the while loops, but the error message still the same...
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Visitor
Visitor
337 Views
Registered: ‎05-22-2020

Re: signal can't be synthesized

Hello dpaul24, I'm just a beginner in HDL, shall I make only "one big process" part Output Function of my FSM?

Thanks in advance!
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Scholar
Scholar
309 Views
Registered: ‎08-07-2014

Re: signal can't be synthesized

What I showed in the docu is Xilinx coding style for FSM inference. It is recommended to follow it.

Now to accept it or not is your choice!

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Xilinx Employee
Xilinx Employee
126 Views
Registered: ‎06-14-2018

Re: signal can't be synthesized

Hi @S_SUPAERO_FR ,

As @bruce_karaffa mentioned issue could be with your loops, indeed those looks incorrect.

while (CLK_100Hz = '1') loop
end loop;

Issue is synthesis cant estimate after how many clock-cycles CLK_100Hz will be asserted, so how many delays has to be inserted, moreover those could be dynamic, hence tool cant infer logic for same.

Could you post your code post removal of loops. Do you still have some checking mechanism for CLK_100z = '1' ?

Thanks,

Ajay

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