05-22-2020 03:41 AM
05-22-2020 03:54 AM
I think the problem is in the while loop. I don't think it is synthesizable. This looks like a software construct. What hardware could the synthesizer build to achieve this loop?
05-22-2020 04:01 AM - edited 05-22-2020 04:03 AM
MY recommended style is the 'one process' style (there are many online articles argumentation on the adv/disadv between 1 and 2 process styles. I don't want to debate on them again here).
Simply follow this document - https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf
Read Chapt 4, "FSM Components", and follow that coding style for correct synthesis results.
05-22-2020 04:11 AM
05-22-2020 04:15 AM
05-22-2020 04:52 AM
What I showed in the docu is Xilinx coding style for FSM inference. It is recommended to follow it.
Now to accept it or not is your choice!
06-06-2020 09:13 AM
Hi @S_SUPAERO_FR ,
As @bruce_karaffa mentioned issue could be with your loops, indeed those looks incorrect.
while (CLK_100Hz = '1') loop
Issue is synthesis cant estimate after how many clock-cycles CLK_100Hz will be asserted, so how many delays has to be inserted, moreover those could be dynamic, hence tool cant infer logic for same.
Could you post your code post removal of loops. Do you still have some checking mechanism for CLK_100z = '1' ?