cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
4,013 Views
Registered: ‎01-22-2015

signals name getting change after synthesis on vivado 2015.4

Jump to solution

Hi All,

 

I have three modules as mentioned below,

 

top_module (it has 4 AXI DMA master engines), arbiter and AXI DMA slave module(MIG user interface). The top_module talking to the arbiter and arbiter talking to the MIG UI. I wanted to add the debug core for output AXI signals of top_module and output AXI signals of the arbiter. After synthesis I opened the schematic and marked required signals for debug from arbiter to MIG UI, while trying to add the top_module to arbiter signals I couldn't find the signals like AWVALID,AWREADY,WVALID,WREADY etc.

But signals are there with different names like mem_q[39:0],D[19:0] etc. The above mentioned AXI signals are may be declared as wire in the DMA engines not reg. 

How to add these signals into ILA core. Please help me.

 

Thanks,

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Moderator
Moderator
7,390 Views
Registered: ‎07-01-2015

Re: signals name getting change after synthesis on vivado 2015.4

Jump to solution

Hi @ramesh.d2015,

 

Can you try putting mark_debug in HDL?

Then use setup debug to add the debug signals.

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

4 Replies
Highlighted
Moderator
Moderator
7,391 Views
Registered: ‎07-01-2015

Re: signals name getting change after synthesis on vivado 2015.4

Jump to solution

Hi @ramesh.d2015,

 

Can you try putting mark_debug in HDL?

Then use setup debug to add the debug signals.

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

View solution in original post

Highlighted
Adventurer
Adventurer
3,998 Views
Registered: ‎01-22-2015

Re: signals name getting change after synthesis on vivado 2015.4

Jump to solution

Hi Arpan,

 

sure, I'll try with mark_debug in the HDL. I didn't try this so far.

Thank you very much, I'll get back to you asap.

 

 

-ramesh 

0 Kudos
Highlighted
Voyager
Voyager
3,988 Views
Registered: ‎10-06-2015

Re: signals name getting change after synthesis on vivado 2015.4

Jump to solution

Another thing to look at is the synthesis settings "flatten_hierarchy" , it may be set to something other than NONE.

Highlighted
Adventurer
Adventurer
3,911 Views
Registered: ‎01-22-2015

Re: signals name getting change after synthesis on vivado 2015.4

Jump to solution

Hi Arpan,

 

Its works perfectly!!!, though the signals are declared as wire in the design I could able to add those into debug core by mark_debug. Thank you very much.

 

 

 

 

 

-ramesh

0 Kudos