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Adventurer
Adventurer
514 Views
Registered: ‎04-22-2016

simple generic memory can be synthesize in xilinx?

Dear All,

I'm trying to implement the below code but I'm not sure whether simple dual port ram generic can implement or not.

 

 SimpleDualPortRAM_generic #(.AddrWidth(3),
                              .DataWidth(53)
                              )
                            dataXMEM_re_0_3 (.clk(clk),
                                             .enb(enb),
                                             .wr_din(xData_re),
                                             .wr_addr(wrXAddr),
                                             .wr_en(wrXEnb),
                                             .rd_addr(rdXAddr),
                                             .rd_dout(xX_re)
                                             );

  SimpleDualPortRAM_generic #(.AddrWidth(3),
                              .DataWidth(53)
                              )
                            dataXMEM_im_0_3 (.clk(clk),
                                             .enb(enb),
                                             .wr_din(xData_im),
                                             .wr_addr(wrXAddr),
                                             .wr_en(wrXEnb),
                                             .rd_addr(rdXAddr),
                                             .rd_dout(xX_im)
                                             );


module SimpleDualPortRAM_generic
(clk,
enb,
wr_din,
wr_addr,
wr_en,
rd_addr,
rd_dout);

parameter AddrWidth = 1;
parameter DataWidth = 1;

input clk;
input enb;
input signed [DataWidth - 1:0] wr_din;
input [AddrWidth - 1:0] wr_addr;
input wr_en;
input [AddrWidth - 1:0] rd_addr;
output signed [DataWidth - 1:0] rd_dout;

reg [DataWidth - 1:0] ram [2**AddrWidth - 1:0];
reg [DataWidth - 1:0] data_int;


always @(posedge clk)
begin
if (enb == 1'b1) begin
if (wr_en == 1'b1) begin
ram[wr_addr] <= wr_din;
end
data_int <= ram[rd_addr];
end
end

assign rd_dout = data_int;

Is this can be synthesize to xilinx FPGA? 

 

0 Kudos
1 Reply
Highlighted
Scholar richardhead
Scholar
452 Views
Registered: ‎08-01-2012

Re: simple generic memory can be synthesize in xilinx?

Your code is a pretty standard inferred dual port ram. 

 

See Synthesis User Guide 901, HDL Coding techniques

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_4/ug901-vivado-synthesis.pdf

 

The templates are pretty similar across Xilinx and Altera/Intel parts. 

 

Are you having any specific issues?