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Visitor dinesh627
Visitor
3,440 Views
Registered: ‎06-26-2017

spartan 3an in system flash programming

sir

i wrote a vhdl code for simple counter. both test bench report and fpga implementation is fine but when i write vhdl code for structural programming using dflip flop . for that test bench report is fine but not working on spartan kit

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Moderator
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Registered: ‎11-09-2015

Re: spartan 3an in system flash programming

Hi @dinesh627,

 

You will need to give more detail if you want help from the community. For example, why aren't you posting your code? Why aren't you explaining why you say it is not working (do you have an error in ISE, do you see an issue on board)?

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-24-2013

Re: spartan 3an in system flash programming

Hi @dinesh627

Before dumping onto the board, did you check the functionality in Simulation (behavioral, post synthesis and implementation)?

Thanks,Vijay
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Visitor dinesh627
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3,412 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

entity updff is
port (rst,clk:in std_logic;
q,qb:inout std_logic_vector(3 downto 0));
end updff;

architecture Behavioral of updff is

component dff is
port(d,rst,clk: in std_logic;
q,qb: inout std_logic);
end component;

signal a,b,c,d,e,f,g,h,i,j : std_logic;

begin

a<=not q(0);
D1 : dff port map(a,rst,clk,q(0),qb(0));

b<=(q(0) xor q(1));
D2 : dff port map(b,rst,clk,q(1),qb(1));

c<= q(0) and q(1)and qb(2);
d<= qb(0) or qb(1);
e<= q(2) and d ;
j<= c or e;
D3 : dff port map(j,rst,clk,q(2),qb(2));

f<= qb(0) or qb(1) or qb(2);
g<= f and q(3);
h<= q(0) and q(1) and q(2) and qb(3);
i<=g or h;
D4 : dff port map(i,rst,clk,q(3),qb(3));

 

end Behavioral;

 

 

 

entity dff is
port(d,rst,clk: in std_logic;
q,qb: inout std_logic);
end dff;
architecture Behavioral of dff is
begin
process (clk, rst)
begin
if (rst='0') then
q<='0';
else
if(clk='1' and clk' event) then
if (d='0') then q<='0';
else q<='1';
end if;
end if;
end if;
end process;
qb<=not q;
end Behavioral;

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Visitor dinesh627
Visitor
3,411 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

NET "rst" LOC = "T9";
NET "CLK" LOC = "E12";
NET "q<3>" LOC = "W21";
NET "q<2>" LOC = "Y22";
NET "q<1>" LOC = "V20";
NET "q<0>" LOC = "V19";

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Visitor dinesh627
Visitor
3,409 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

bit file is generated. pin allocation is done. there is no error in simulation. pinout report of xilinx is okay. But in spartan 3an starter kit it is not working. and no error and no warning is showing. without using the component for the simple counter spartan 3 an is simulating. i have posted the code for counter using d_flip flop

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Visitor dinesh627
Visitor
3,402 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

Hello @florentw i have posted the code of counter using Dflipflop. Everything is okay before the dumping the code on spartan kit.

simulation test bench in producing the required output. ucf code is also posted. please tell if any.

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Visitor dinesh627
Visitor
3,377 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

please help

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Moderator
Moderator
3,372 Views
Registered: ‎11-09-2015

Re: spartan 3an in system flash programming

Hi @dinesh627,

 

As mentioned by @vijayak, did you check the post-implementation simulation? Could you show the waveforms of behavioral and post-implementation showing the behavior

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor dinesh627
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3,367 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

 
screenshot_20170627_165432.jpg
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Visitor dinesh627
Visitor
3,403 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

sir this is my ucf file

screenshot_20170627_165326.jpg
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Visitor dinesh627
Visitor
3,402 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

Sir @florentw

this output should be reflected on fpga spartan 3an starter kit board. when i dump the code on board all four led glow. I am not getting the desired output as shown in test bench report.

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Moderator
Moderator
3,399 Views
Registered: ‎11-09-2015

Re: spartan 3an in system flash programming

@dinesh627,

 

Is it post-implementation simulation or behavioral? Please clarify


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor dinesh627
Visitor
3,396 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

behavioral

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Moderator
Moderator
3,394 Views
Registered: ‎11-09-2015

Re: spartan 3an in system flash programming

Hi @dinesh627,

 

So please show the post-implementation simulation


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor dinesh627
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Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

@florentw

 

its a behavioral simulation

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Visitor dinesh627
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Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

@florentw

how to get the post implementation simulation. as m working on Xilinx 14.7

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Moderator
Moderator
3,382 Views
Registered: ‎11-09-2015

Re: spartan 3an in system flash programming

Hi @dinesh627,

 

See these links:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/pp_p_process_generate_post_place_and_route_simulation_model.htm

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx14_4/ise_tutorial_ug695.pdf


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor dinesh627
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Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

@florentw

 

I already did this. generated ucf file.

screenshot_20170628_155751.jpg
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Visitor dinesh627
Visitor
3,378 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

Place and route

generated post simulation. there is no error there.

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Moderator
Moderator
3,437 Views
Registered: ‎11-09-2015

Re: spartan 3an in system flash programming

Hi @dinesh627,

 

generated post simulation. there is no error there.

-> please show the screenshot... (run the simulation!)


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor dinesh627
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Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

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Moderator
Moderator
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Registered: ‎03-16-2017

Re: spartan 3an in system flash programming

Hi @dinesh627

 

 Post PNR simulation:Capture.PNG

Regards,
hemangd

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Moderator
Moderator
3,420 Views
Registered: ‎11-09-2015

Re: spartan 3an in system flash programming

Hi @dinesh627,

 

Please run the simulation.

 

Refer to UG695 p126 (Timing Simulation Using Xilinx ISim) and share the screenshot of the post implementation simulation waveform


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor dinesh627
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Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

@florentw

 

Thankyou for guiding me upto postsimulation result

here is the post simulation result

screenshot_20170628_161345.jpg
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Visitor dinesh627
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3,412 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

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Visitor dinesh627
Visitor
3,407 Views
Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

@florentw

simulation post place & route

screenshot_20170628_161904.jpg
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Moderator
Moderator
3,391 Views
Registered: ‎11-09-2015

Re: spartan 3an in system flash programming

Hi @dinesh627,

 

Thanks. Just a check: Do you have the same UCF between the working project and the non-working?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Visitor dinesh627
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Registered: ‎06-26-2017

Re: spartan 3an in system flash programming

@florentw yes sir same working ucf

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Moderator
Moderator
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Registered: ‎11-09-2015

Re: spartan 3an in system flash programming

@dinesh627,

 

Then you should try to add an ILA to see what is going on in the HW


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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