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1,896 Views
Registered: ‎02-09-2018

srl_style dosen't affect the synthesize

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Hi,

 

I synthesized the following verilog code, but the shift registers are still used even with the attribute (* srl_style = "register" *).

what is wrong?

 

module srl_test(
    input wire [3:0] in,
    input wire clk,
    output reg [3:0] out
    );
 
    (* srl_style = "register" *) reg [3:0] reg0;
    (* srl_style = "register" *) reg [3:0] reg1;
    (* srl_style = "register" *) reg [3:0] reg2;
    (* srl_style = "register" *) reg [3:0] reg3;
   
    always @( posedge clk )
    begin
     reg0 <= in;
     reg1 <= reg0;
     reg2 <= reg1;
     reg3 <= reg2;
     out <= reg3;
    end
endmodule

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syedz
Moderator
Moderator
2,343 Views
Registered: ‎01-16-2013

@elsayed.abdellah,

 

CR-996079 has been filed and the issue is reported to the factory. 

 

--Syed

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syedz
Moderator
Moderator
1,885 Views
Registered: ‎01-16-2013

@elsayed.abdellah,


Checked in Vivado 2017.4 and lt doesnt seem to honour the attribute. 

Capture.JPG

Looks like a bug to me, Will check with Factory and get back to you.

 

The example attached in the below link works as expected.

https://www.xilinx.com/support/answers/60799.html

 

--Syed

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Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
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1,875 Views
Registered: ‎02-09-2018
Yes, this is exactly what I got.
So, it was very confusing.
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aher
Xilinx Employee
Xilinx Employee
1,865 Views
Registered: ‎07-21-2014
Hi,

This behavior is reported as bug and should be resolved in later build.
However as Syed pointed out, will you be able to use the example in AR as a workaround for now?

-Shreyas
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syedz
Moderator
Moderator
2,344 Views
Registered: ‎01-16-2013

@elsayed.abdellah,

 

CR-996079 has been filed and the issue is reported to the factory. 

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------

View solution in original post

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1,794 Views
Registered: ‎02-09-2018
Yes, the example in AR works well.
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