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Newbie latha@2017
Newbie
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Registered: ‎06-24-2018

suggestions to clear warnings during synthesis

module twodtdc(reset,out,clk);
parameter M=3,N=4;
wire [M-1:0]in;
output[M-1:0]out;
input clk,reset;
wire [M*(N-1):1]t;
/*generate
genvar i;
for(i=1;i<=8;i=i+1)
begin:K */
graycounter g1(in,clk,reset);
dffn #(M) p[1:N]({out,t},{t,in},clk);
//end
//endgenerate
endmodule

module graycounter(Q, clk, reset);
parameter n=6; // Number of T flip-flops
output[n:1]Q; reg [n:1]Q; // Register all procedure outputs.
input clk, reset;
always @(posedge clk or posedge reset)
if (reset) Q<=0;
else begin
// Q[1] <= (Q 6?Q5?Q4?Q3?Q2); // ?This one is a D -FF.
Q[1] <= (~(^Q[n:2]));
// Toggle FF statements
// Q2 <= IF( (Q6?Q5?Q4?Q 3?Q2)&Q1) THEN Q2 : ELSE Q2;
Q[2] <= (~(^Q[n:2])&Q[1]) ? ~Q[2] : Q[2];
// Q3 <= IF (Q6?Q5?Q4?Q3)&Q 2&(~Q1)) THEN Q3 : ELSE Q3;
Q[3] <= (~(^Q[n:3]))&Q[2]&(~|Q[1]) ? ~Q[3] : Q[3];
// Q4 <= IF(Q6?Q5?Q4)&Q3&Q2&Q1) THEN Q4 : ELSE Q4;
Q[4] <= (~(^Q[n:4]))&Q[n-3]&(~|Q[n-4:1]) ? ~Q[4] : Q[4];
// Q5 <= IF((Q6?Q5)&Q4&Q3 &Q2&Q1) THEN Q5 : ELSE Q5;
Q[5] <= (~(^Q[n:5]))&Q[n-2]&(~|Q[n-3:1]) ? ~Q[5] : Q[5];
// Q6 <=IF(Q6?Q5)&Q4&Q3&Q2&Q1) THEN Q6 : ELSE Q6;
Q[6] <= (^Q[n:5])&(~|Q[n-2:1]) ? ~Q[6] : Q[6];
end // else
endmodule // Gray

module dffn(q,d,clk);
parameter bits=6;
input [bits-1:0]d;
output[bits-1:0]q;
input clk;
dff DFF[bits-1:0](q,d,clk);
endmodule

 


module dff(q,d,clk);
output q;
input d,clk;
reg q;
initial q=0;
always@(posedge clk)
q<=d^0^1;
endmodule

Warnings:

HDLCompiler:189 - "D:\Xilinx\encoder\twodtdc.v" Line 32: Size mismatch in connection of port <Q>. Formal port size is 6-bit while actual signal size is 3-bit.

HDLCompiler:413 - "D:\Xilinx\encoder\twodtdc.v" Line 78: Result of 32-bit expression is truncated to fit in 1-bit target.

 

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