09-21-2009 04:58 AM
My project consists essentially of 3 components connected together structurally, from which I want to create a higher level component. Because the system was too large to synthesise on a 32 bit operating system, I have synthesised each of the components and used the NGC files in the main system, in place of the VHDL code (so using black boxes instead of re-synthesising any of this)
The project synthesises without any errors and the only warnings are "instantiating black boxmodule"
however, the results are very suspicious
call the three systems System A, B and C, and the overall structural system is System C
System A uses
7168 slice registers
21054 slice LUTs
System B uses
8960 slice registers
13602 slice LUTs
System C uses
18271 slice registers
5476 slice LUTs
and the overall system of these combined (System D) uses
18270 slice registers
5425 slice LUTs
so apparently by combining these components, the system now uses less resources, which doesnt really make any sense.
Does anyone have any knowledge on this matter or advice they can lend me please?
09-22-2009 06:18 AM
Are you looking at the logic utilization from the synthesis report or map report? I would double check the reports to make sure that all sub-blocks are connected correctly and NOT optimized away.
09-23-2009 06:27 AM
Yes I am looking at the synthesis report and it is optimising. I have "optimise instantiated primitives" turned off. How do I stop the synthesiser from optimising this component, and just use as black box?
09-25-2009 12:23 PM
If all the blackboxes are connected properly (i.e. all inputs to them are driven and all outputs are used by other blocks/logic). xst shouldn't optimize them away. The other thing you could try is to turn off the "Read Cores" option under "Synthesis Option" of XST properties window.
By the way, "optimise instantiated primitives" options is for FPGA primitives not user blackboxes.