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Observer bujosa
Observer
3,478 Views
Registered: ‎05-24-2011

synplify_pro changes cell name in edf when module uses parameters

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my verilog rtl hierarchy is top.v which instantiates modules in sub1.v, sub2.v, etc.

 

I create a edf for the top.v, sub1.v, sub2.v, etc.  When I want to build the whole chip I read in all the *.edf into ISE.  When I am interested in only one sub block I build with top.edf and sub1.edf for example.  I do this for faster builds during development. This works fine.

 

Then I added parameters to one of the sub blocks.  So in top.v,  sub1 is instantiated like this sub1 # (parameter clkref = 200) u_sub1 ();

 

This fails in ISE because synplify_pro changes the cell name when writing out top.edf.  Instead of (cell sub1 (cellType GENERIC) synplify_pro writes out (cell sub1_Z1 (cellTYpe GENERIC).   So when I read top.edf into ISE, ISE looks for sub1_Z1.edf instead of sub1.edf.  I confirmed this by manually editing the top.edf removing the "_Z1" from the cell name and everything build fine. 

 

For now my work around is to not declare the parameters in top.v and default the parameters to the correct value in sub1.  This is a hack though.

 

My question is, how do I prevent synplify_pro from changing the cell name of the instantiated module when writing out the edf?  Funny thing is that when I write out the netlist as verilog top_gates.v the module name is correct.  Only top.edf is affected.

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Xilinx Employee
Xilinx Employee
4,264 Views
Registered: ‎11-28-2007

Re: synplify_pro changes cell name in edf when module uses parameters

Jump to solution

I don't know how to prevent synplify_pro from changing the cell name of the instantiated module. You may want to ask Synopsys about that. However, why do you pass parameters to an already synthesized module since the parameters are not going to change the edf for the submodules anyway? If you want to be able to switch between full synthesis and modular synthesis, you may want to look into compile points in Synplify.

 


@bujosa wrote:

 

my verilog rtl hierarchy is top.v which instantiates modules in sub1.v, sub2.v, etc.

 

I create a edf for the top.v, sub1.v, sub2.v, etc.  When I want to build the whole chip I read in all the *.edf into ISE.  When I am interested in only one sub block I build with top.edf and sub1.edf for example.  I do this for faster builds during development. This works fine.

 

Then I added parameters to one of the sub blocks.  So in top.v,  sub1 is instantiated like this sub1 # (parameter clkref = 200) u_sub1 ();

 

This fails in ISE because synplify_pro changes the cell name when writing out top.edf.  Instead of (cell sub1 (cellType GENERIC) synplify_pro writes out (cell sub1_Z1 (cellTYpe GENERIC).   So when I read top.edf into ISE, ISE looks for sub1_Z1.edf instead of sub1.edf.  I confirmed this by manually editing the top.edf removing the "_Z1" from the cell name and everything build fine. 

 

For now my work around is to not declare the parameters in top.v and default the parameters to the correct value in sub1.  This is a hack though.

 

My question is, how do I prevent synplify_pro from changing the cell name of the instantiated module when writing out the edf?  Funny thing is that when I write out the netlist as verilog top_gates.v the module name is correct.  Only top.edf is affected.




Cheers,
Jim
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1 Reply
Xilinx Employee
Xilinx Employee
4,265 Views
Registered: ‎11-28-2007

Re: synplify_pro changes cell name in edf when module uses parameters

Jump to solution

I don't know how to prevent synplify_pro from changing the cell name of the instantiated module. You may want to ask Synopsys about that. However, why do you pass parameters to an already synthesized module since the parameters are not going to change the edf for the submodules anyway? If you want to be able to switch between full synthesis and modular synthesis, you may want to look into compile points in Synplify.

 


@bujosa wrote:

 

my verilog rtl hierarchy is top.v which instantiates modules in sub1.v, sub2.v, etc.

 

I create a edf for the top.v, sub1.v, sub2.v, etc.  When I want to build the whole chip I read in all the *.edf into ISE.  When I am interested in only one sub block I build with top.edf and sub1.edf for example.  I do this for faster builds during development. This works fine.

 

Then I added parameters to one of the sub blocks.  So in top.v,  sub1 is instantiated like this sub1 # (parameter clkref = 200) u_sub1 ();

 

This fails in ISE because synplify_pro changes the cell name when writing out top.edf.  Instead of (cell sub1 (cellType GENERIC) synplify_pro writes out (cell sub1_Z1 (cellTYpe GENERIC).   So when I read top.edf into ISE, ISE looks for sub1_Z1.edf instead of sub1.edf.  I confirmed this by manually editing the top.edf removing the "_Z1" from the cell name and everything build fine. 

 

For now my work around is to not declare the parameters in top.v and default the parameters to the correct value in sub1.  This is a hack though.

 

My question is, how do I prevent synplify_pro from changing the cell name of the instantiated module when writing out the edf?  Funny thing is that when I write out the netlist as verilog top_gates.v the module name is correct.  Only top.edf is affected.




Cheers,
Jim
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