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Fox55623
Newbie
Newbie
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Registered: ‎07-18-2021

[synth 8-223] declone instance

Hi, everyone I'm new in Vivado development FPGA.

When I write a simple division module in Vivado and tried to synthesis it in Vivado 2020.2.

It shows an information read 

[Synth 8-223] decloning instance 'U_K0' (div) to 'U_K1' (4 more like this)
  [Synth 8-223] decloning instance 'U_K0' (div) to 'U_K2'
  [Synth 8-223] decloning instance 'U_K0' (div) to 'U_K3'
  [Synth 8-223] decloning instance 'U_K0' (div) to 'U_K4'
  [Synth 8-223] decloning instance 'U_K0' (div) to 'U_K5'

 

BUT in my div module it connect  in different signal.  Can anyone solve this problem?

 

    div U_K0(
        .clk                ( clk              ),
        .rst                ( rst              ),
        .dividend_43        ( dividend_52_SX0  ), // SX   43+9=52 
        .divisor_26         ( divisor_17       ), // XSXr 26-9=17 
        .qouent_24          ( qouent_24_div0   ), // K    52 -> 24.20
        .start              ( start            ),
        .valid              ( valid_div_0      )
    );
    div U_K1(
        .clk                ( clk              ),
        .rst                ( rst              ),
        .dividend_43        ( dividend_52_SX1  ), // SX   43+9=52 
        .divisor_26         ( divisor_17       ), // XSXr 26-9=17 
        .qouent_24          ( qouent_24_div1   ), // K    52 -> 24.20
        .start              ( start            ),
        .valid              ( valid_div_1      )
    );
    div U_K2(
        .clk                ( clk              ),
        .rst                ( rst              ),
        .dividend_43        ( dividend_52_SX2  ), // SX   43+9=52 
        .divisor_26         ( divisor_17       ), // XSXr 26-9=17 
        .qouent_24          ( qouent_24_div2   ), // K    52 -> 24.20
        .start              ( start            ),
        .valid              ( valid_div_2      )
    );
    div U_K3(
        .clk                ( clk              ),
        .rst                ( rst              ),
        .dividend_43        ( dividend_52_SX3  ), // SX   43+9=52 
        .divisor_26         ( divisor_17       ), // XSXr 26-9=17 
        .qouent_24          ( qouent_24_div3   ), // K    52 -> 24.20
        .start              ( start            ),
        .valid              ( valid_div_3      )
    );
    div U_K4(
        .clk                ( clk              ),
        .rst                ( rst              ),
        .dividend_43        ( dividend_52_SX4  ), // SX   43+9=52 
        .divisor_26         ( divisor_17       ), // XSXr 26-9=17 
        .qouent_24          ( qouent_24_div4   ), // K    52 -> 24.20
        .start              ( start            ),
        .valid              ( valid_div_4      )
    );
    div U_K5(
        .clk                ( clk              ),
        .rst                ( rst              ),
        .dividend_43        ( dividend_52_SX5  ), // SX   43+9=52 
        .divisor_26         ( divisor_17       ), // XSXr 26-9=17 
        .qouent_24          ( qouent_24_div5   ), // q    52 -> 24.20  K
        .start              ( start            ),
        .valid              ( valid_div_5      )
    );
wire  [51:0]    dividend_52_SX0, dividend_52_SX1, dividend_52_SX2, dividend_52_SX3, dividend_52_SX4, dividend_52_SX5;
    
wire  [16:0]    divisor_17;
wire  [51:0]    qouent_24_div0, qouent_24_div1, qouent_24_div2, qouent_24_div3, qouent_24_div4, qouent_24_div5;

wire            valid_div_0, valid_div_1, valid_div_2, valid_div_3, valid_div_4, valid_div_5;
wire            start;

 

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