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Turkey9999999
Observer
Observer
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Registered: ‎11-11-2020

synthesis bug: flipping order of nibble using for loop

Trying to flip order of nibbles using a for loop but getting out of range when synthesizing in vivado, in contrast the vivado simulation says its in range.

Attached is my vivado.2020 project as a ZIP file...  

Any ideas how to work around this problem?

 

Log:

  • [Synth 8-524] part-select [67:64] out of range of prefix 'data' ["C:/Users/xxx/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v":39]
  •  

Synth log:

---------------------------------------------------------------------------------
Starting Synthesize : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1021.457 ; gain = 0.000
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'testcase' [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:70]
Parameter max_cw bound to: 8 - type: integer
Parameter max_dw bound to: 64 - type: integer
Parameter max_sw bound to: 4 - type: integer
WARNING: [Synth 8-6896] loop limit (65536) exceeded inside initial block, initial block items will be ignored [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:85]
WARNING: [Synth 8-6896] event control except as first statement of always block inside initial block, initial block items will be ignored [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:93]
WARNING: [Synth 8-6896] wait statement is inside initial block, initial block items will be ignored [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:117]
INFO: [Synth 8-6157] synthesizing module 'synth_bug' [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:4]
Parameter max_cw bound to: 8 - type: integer
Parameter max_dw bound to: 64 - type: integer
Parameter max_sw bound to: 4 - type: integer
INFO: [Synth 8-251] flip: flip[x] = data[0] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 3:0]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[1] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 7:4]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[2] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 11:8]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[3] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 15:12]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[4] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 19:16]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[5] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 23:20]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[6] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 27:24]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[7] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 31:28]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[8] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 35:32]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[9] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 39:36]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[10] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 43:40]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[11] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 47:44]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[12] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 51:48]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[13] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 55:52]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[14] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 59:56]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
INFO: [Synth 8-251] flip: flip[x] = data[15] = x (date=xxxxxxxxxxxxxxxx) [[j*4 + 4 = x:x]] [[i*4 + 4 = 63:60]] [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:41]
ERROR: [Synth 8-524] part-select [67:64] out of range of prefix 'data' [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:39]
ERROR: [Synth 8-6156] failed synthesizing module 'synth_bug' [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:4]
ERROR: [Synth 8-6156] failed synthesizing module 'testcase' [C:/Users/wmoore/Documents/fpga/zynq_pl/rtl/vlog/synth_bug/syn_testcase1.v:70]

 

 

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3 Replies
markcurry
Scholar
Scholar
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Registered: ‎09-16-2009

Well, not the answer you're looking for, but you need to start out by recoding the 'for' loop.

In RTL design 'for' loops must have elaboration-time constants for the boundary conditions.  Said in software-speak, all 'for' loops must be unrollable.  

Vivado should have just emitted an error message on that before proceeding any further.  Start with recoding for that problem before continuing.

Regards,

Mark

Turkey9999999
Observer
Observer
371 Views
Registered: ‎11-11-2020

Thanks.  You were right.  Now it passes synthesis:

 

//------------------------------------------------------------------
// => flip :reverse order of nibbles of a word of a specified size
//------------------------------------------------------------------
function [max_dw-1:0] nibble_flip(
    input [max_sw-1:0] size,
    input [max_dw-1:0] data
);
begin :nibble_flip_i
    integer             i;
    integer             j;
    integer             len;  
    reg [max_dw+4-1:0]  tmp;
    
    len = (size*2 > max_dw/4) ? (max_dw/4) : size*2;   
    tmp = {max_dw{1'b0}};
    
    for(i=0; i < max_dw/4; i=i+1) begin
        j            = len-i-1;     
		
		if (i < len) begin
            tmp[j*4 +:4] = data[i*4 +:4];
        
            // Synthesis_translate off
            $display("flip: flip[%0d] = data[%0d] = %0x  (date=%x) [[j*4 + 4 = %0d:%0d]] [[i*4 + 4 = %0d:%0d]]", 
                j, i, tmp[j*4 +:4], 
			    data, 
			    j*4 + 4 -1, 
			    j*4, 			
			    i*4 + 4 -1,
			    i*4
		    );
            // Synthesis_translate on		    
		end
    end 
    
    nibble_flip = tmp[max_dw-1:0];
end endfunction
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markcurry
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Registered: ‎09-16-2009

Just for completeness sake for anyone reading along, the loop was unrollable, because the max condition was based on a net variable (a function of input wire usr_csize) .  This is not allowed.  Your changes made the loop conditionals all elaboration-time constants, and things worked.

Regards,

Mark

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