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Contributor
Contributor
985 Views
Registered: ‎06-24-2019

synthesis out-of-date

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When synthesis is finished,it showed synthesis out-of-date again.

Screen Shot 2019-07-03 at 1.59.31 PM.png

And from other similar question,I tried the command 'get_property NEEDS_REFRESH [get_runs <run_name>]' , it indeed returned 1.I have saved the design and make sure the verilog files in project are up-to-date. I don't know why this is still happen.What should I do?

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Xilinx Employee
Xilinx Employee
969 Views
Registered: ‎02-27-2019

Hi @yinglu2 ,

  You can click the details to find what results in it .

  Capture.PNG 

  When running synthesis , aviod modifying your sources.

Yang

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Moderator
Moderator
972 Views
Registered: ‎03-16-2017

Hi @yinglu2 , 

Have a look into this thread. https://forums.xilinx.com/t5/Implementation/synthesis-and-implementation-out-of-date/td-p/456968

It may help you out. 

Regards,
hemangd

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Highlighted
Xilinx Employee
Xilinx Employee
970 Views
Registered: ‎02-27-2019

Hi @yinglu2 ,

  You can click the details to find what results in it .

  Capture.PNG 

  When running synthesis , aviod modifying your sources.

Yang

-------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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Observer
Observer
925 Views
Registered: ‎06-19-2019
as yangc mentioned, the best way is by clicking the details button.
sometimes it is just the file order but it is better to make sure.
if u c that u have a file changed that is not important or if it is only a file order issue the press the force up to date button.
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Moderator
Moderator
913 Views
Registered: ‎03-16-2017

Hi @yinglu2 , 

Do you have further queries on it? 

Else, close the thread by marking it as accepted solution. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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