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Visitor
Visitor
368 Views
Registered: ‎11-06-2018

synthesis resource utilization

Hi,

 

I'm using vivado to synthesis my design.It's quite huge and the synthesis utilization reports most of the  design is synthesised into LUT while few DSP. In order to hold the entile design, I doubt if there's option in the tool with which I can synthesis rtl into DSP?

 

Thanks!

 

Best,

 

Sophie

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3 Replies
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Xilinx Employee
Xilinx Employee
365 Views
Registered: ‎05-22-2018

Hi @fmq223847 ,

You can try to use USE_DSP attribute.

USE_DSP instructs the synthesis tool how to deal with synthesis arithmetic structures.
By default, unless there are timing concerns or threshold limits, synthesis attempts to infer
mults, mult-add, mult-sub, and mult-accumulate type structures into DSP blocks.

By default  adders, subtracters and accumulator are implemented with the logic instead of with DSP blocks. The USE_DSP attribute overrides the default behavior and force these structures into DSP blocks.

Refernce link (Page No.66):

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf

Thanks,

Raj

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Visitor
Visitor
325 Views
Registered: ‎11-06-2018

Thank you Raj !  I'll try it.

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Xilinx Employee
Xilinx Employee
321 Views
Registered: ‎05-22-2018

Hi @fmq223847 ,

Do you have further queries on this? If not, please close this thread by marking it as accepted solution.

Thanks,

Raj 

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