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hycheah
Participant
Participant
5,531 Views
Registered: ‎02-27-2010

synthesis translate_on/off : coregen vs manual instantiation

There are 2 ways I can design a multiplier using the DSP48E1 primitive:

 

1. Using Coregen (enable use of DSP slices)

2. Instantiate the DSP48E1 manually from Language Template

 

When I looked at the .v design file generated by Coregen, I noticed that the construct // synthesis translate_off and // synthesis translate_on is placed before and after a DSP48E1 instantiation.

 

// synthesis translate_off

   <<some wire declarations and assign statements>>
  
    DSP48E1 #(
    .USE_DPORT ( "FALSE" ),
    .ADREG ( 0 ),
    .B_INPUT ( "DIRECT" ),
    .PATTERN ( 48'h000000000000 ),
    .AREG ( 0 ),
    .ACASCREG ( 0 ),
    .BREG ( 0 ),
    .MREG ( 0 ),
    .PREG ( 1 ),
    .CARRYINREG ( 0 ),
    .OPMODEREG ( 0 ),
    .ALUMODEREG ( 0 ),
    .CARRYINSELREG ( 0 ),
    .INMODEREG ( 0 ),
    .USE_MULT ( "MULTIPLY" ),
    .A_INPUT ( "DIRECT" ),
    .BCASCREG ( 0 ),
    .CREG ( 0 ),
    .DREG ( 0 ),
    .SEL_PATTERN ( "PATTERN" ),
    .SEL_MASK ( "MASK" ),
    .USE_PATTERN_DETECT ( "NO_PATDET" ),
    .MASK ( 48'h3fffffffffff ),
    .USE_SIMD ( "ONE48" ),
    .AUTORESET_PATDET ( "NO_RESET" ))
  \blk00000003/blk00000006  (
    .PATTERNBDETECT(\NLW_blk00000003/blk00000006_PATTERNBDETECT_UNCONNECTED ),
    .RSTC(\blk00000003/sig00000022 ),
    .CEB1(\blk00000003/sig00000022 ),
    .CEAD(\blk00000003/sig00000022 ),
    .MULTSIGNOUT(\NLW_blk00000003/blk00000006_MULTSIGNOUT_UNCONNECTED ),
    .CEC(\blk00000003/sig00000022 ),
    .RSTM(\blk00000003/sig00000022 ),
    .MULTSIGNIN(\NLW_blk00000003/blk00000006_MULTSIGNIN_UNCONNECTED ),
    .CEB2(\blk00000003/sig00000022 ),
    .RSTCTRL(\blk00000003/sig00000022 ),
    .CEP(\blk00000003/sig00000043 ),
    .CARRYCASCOUT(\NLW_blk00000003/blk00000006_CARRYCASCOUT_UNCONNECTED ),
    .RSTA(\blk00000003/sig00000022 ),
    .CECARRYIN(\blk00000003/sig00000022 ),
    .UNDERFLOW(\NLW_blk00000003/blk00000006_UNDERFLOW_UNCONNECTED ),
    .PATTERNDETECT(\NLW_blk00000003/blk00000006_PATTERNDETECT_UNCONNECTED ),
    .RSTALUMODE(\blk00000003/sig00000022 ),
    .RSTALLCARRYIN(\blk00000003/sig00000022 ),
    .CED(\blk00000003/sig00000022 ),
    .RSTD(\blk00000003/sig00000022 ),
    .CEALUMODE(\blk00000003/sig00000022 ),
    .CEA2(\blk00000003/sig00000022 ),
    .CLK(clk),
    .CEA1(\blk00000003/sig00000022 ),
    .RSTB(\blk00000003/sig00000022 ),
    .OVERFLOW(\NLW_blk00000003/blk00000006_OVERFLOW_UNCONNECTED ),
    .CECTRL(\blk00000003/sig00000022 ),
    .CEM(\blk00000003/sig00000022 ),
    .CARRYIN(\blk00000003/sig00000022 ),
    .CARRYCASCIN(\NLW_blk00000003/blk00000006_CARRYCASCIN_UNCONNECTED ),
    .RSTINMODE(\blk00000003/sig00000022 ),
    .CEINMODE(\blk00000003/sig00000022 ),
    .RSTP(\blk00000003/sig00000022 ),
    .ACOUT({\NLW_blk00000003/blk00000006_ACOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<28>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<26>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<24>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<22>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<20>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<18>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<16>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<14>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<12>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<10>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<8>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<6>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<4>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<2>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACOUT<0>_UNCONNECTED }),
    .OPMODE({\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000043 , 
\blk00000003/sig00000022 , \blk00000003/sig00000043 }),
    .PCIN({\NLW_blk00000003/blk00000006_PCIN<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<46>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<44>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<43>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<42>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<40>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<38>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<37>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<36>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<34>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<32>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<31>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<30>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<28>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<26>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<24>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<22>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<20>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<18>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<16>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<14>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<12>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<10>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<8>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<6>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<4>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<2>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCIN<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCIN<0>_UNCONNECTED }),
    .ALUMODE({\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 }),
    .C({\NLW_blk00000003/blk00000006_C<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<46>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<44>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<43>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<42>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<40>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<38>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<37>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<36>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<34>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<32>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<31>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<30>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<28>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<26>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<25>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<24>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<22>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<20>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<19>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<18>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<16>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<14>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<13>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<12>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<10>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<8>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<7>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<6>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<4>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<2>_UNCONNECTED , \NLW_blk00000003/blk00000006_C<1>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_C<0>_UNCONNECTED }),
    .CARRYOUT({\NLW_blk00000003/blk00000006_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_CARRYOUT<2>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_CARRYOUT<0>_UNCONNECTED }),
    .INMODE({\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000043 , \blk00000003/sig00000022 , \blk00000003/sig00000022 }),
    .BCIN({\NLW_blk00000003/blk00000006_BCIN<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCIN<16>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCIN<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCIN<14>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCIN<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCIN<12>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCIN<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCIN<10>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCIN<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCIN<8>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCIN<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCIN<6>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCIN<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCIN<4>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCIN<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCIN<2>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCIN<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCIN<0>_UNCONNECTED }),
    .B({b_1[15], b_1[15], b_1[15], b_1[14], b_1[13], b_1[12], b_1[11], b_1[10], b_1[9], b_1[8], b_1[7], b_1[6], b_1[5], b_1[4], b_1[3], b_1[2], b_1[1]
, b_1[0]}),
    .BCOUT({\NLW_blk00000003/blk00000006_BCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<16>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<14>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<12>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<10>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<8>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<6>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<4>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<2>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_BCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_BCOUT<0>_UNCONNECTED }),
    .D({\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , 
\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , 
\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , 
\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , 
\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 }),
    .P({\NLW_blk00000003/blk00000006_P<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<46>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_P<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<44>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<43>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_P<42>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<40>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_P<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<38>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<37>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_P<36>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<34>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_P<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_P<32>_UNCONNECTED , p_2[31], p_2[30], p_2[29], p_2[28], p_2[27], p_2[26]
, p_2[25], p_2[24], p_2[23], p_2[22], p_2[21], p_2[20], p_2[19], p_2[18], p_2[17], p_2[16], p_2[15], p_2[14], p_2[13], p_2[12], p_2[11], p_2[10], 
p_2[9], p_2[8], p_2[7], p_2[6], p_2[5], p_2[4], p_2[3], p_2[2], p_2[1], p_2[0]}),
    .A({\NLW_blk00000003/blk00000006_A<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_A<28>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_A<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_A<26>_UNCONNECTED , \NLW_blk00000003/blk00000006_A<25>_UNCONNECTED , 
\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , 
\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 , a_0[15], a_0[14], a_0[13], a_0[12], 
a_0[11], a_0[10], a_0[9], a_0[8], a_0[7], a_0[6], a_0[5], a_0[4], a_0[3], a_0[2], a_0[1], a_0[0]}),
    .PCOUT({\NLW_blk00000003/blk00000006_PCOUT<47>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<46>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<45>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<44>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<43>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<42>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<41>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<40>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<39>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<38>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<37>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<36>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<35>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<34>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<33>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<32>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<31>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<30>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<28>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<26>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<24>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<22>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<20>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<18>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<16>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<14>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<12>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<10>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<8>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<6>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<4>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<2>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_PCOUT<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_PCOUT<0>_UNCONNECTED }),
    .ACIN({\NLW_blk00000003/blk00000006_ACIN<29>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<28>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<27>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<26>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<25>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<24>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<23>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<22>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<21>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<20>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<19>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<18>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<17>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<16>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<15>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<14>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<13>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<12>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<11>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<10>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<9>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<8>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<7>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<6>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<5>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<4>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<3>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<2>_UNCONNECTED , 
\NLW_blk00000003/blk00000006_ACIN<1>_UNCONNECTED , \NLW_blk00000003/blk00000006_ACIN<0>_UNCONNECTED }),
    .CARRYINSEL({\blk00000003/sig00000022 , \blk00000003/sig00000022 , \blk00000003/sig00000022 })
  );
  VCC   \blk00000003/blk00000005  (
    .P(\blk00000003/sig00000043 )
  );
  GND   \blk00000003/blk00000004  (
    .G(\blk00000003/sig00000022 )
  );

// synthesis translate_on

 

 

However these constructs are not present from the Language Template of DSP48E1.

//  <-----Cut code below this line---->

   // DSP48E1: 48-bit Multi-Functional Arithmetic Block
   //          Virtex-6
   // Xilinx HDL Language Template, version 12.2

   DSP48E1 #(
      .ACASCREG(1),                     // Number of pipeline registers between A/ACIN input and ACOUT output,
                                        // 0, 1, or 2
      .ADREG(1),                        // Number of pipeline registers on pre-adder output, 0 or 1
      .ALUMODEREG(1),                   // Number of pipeline registers on ALUMODE input, 0 or 1
      .AREG(1),                         // Number of pipeline registers on the A input, 0, 1 or 2
      .AUTORESET_PATDET("NO_RESET"),    // NO_RESET, RESET_MATCH, RESET_NOT_MATCH
      .A_INPUT("DIRECT"),               // Selects A input used, "DIRECT" (A port) or "CASCADE" (ACIN port)
      .BCASCREG(1),                     // Number of pipeline registers between B/BCIN input and BCOUT output,
                                        // 0, 1, or 2
      .BREG(1),                         // Number of pipeline registers on the B input, 0, 1 or 2
      .B_INPUT("DIRECT"),               // Selects B input used, "DIRECT" (B port) or "CASCADE" (BCIN port)
      .CARRYINREG(1),                   // Number of pipeline registers for the CARRYIN input, 0 or 1
      .CARRYINSELREG(1),                // Number of pipeline registers for the CARRYINSEL input, 0 or 1
      .CREG(1),                         // Number of pipeline registers on the C input, 0 or 1
      .DREG(1),                         // Number of pipeline registers on the D input, 0 or 1
      .INMODEREG(1),                    // Number of pipeline registers on INMODE input, 0 or 1
      .MASK(48'h3fffffffffff),          // 48-bit Mask value for pattern detect
      .MREG(1),                         // Number of multiplier pipeline registers, 0 or 1
      .OPMODEREG(1),                    // Number of pipeline registers on OPMODE input, 0 or 1
      .PATTERN(48'h000000000000),       // 48-bit Pattern match for pattern detect
      .PREG(1),                         // Number of pipeline registers on the P output, 0 or 1
      .SEL_MASK("MASK"),                // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2" 
      .SEL_PATTERN("PATTERN"),          // Select pattern value between the "PATTERN" value or the value on the
                                        // "C" port
      .USE_DPORT("FALSE"),              // Select D port usage, TRUE or FALSE
      .USE_MULT("MULTIPLY"),            // Select multiplier usage, "MULTIPLY", "DYNAMIC", or "NONE" (no
                                        // multiplier)
      .USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect, "PATDET", "NO_PATDET" 
      .USE_SIMD("ONE48")                // SIMD selection, "ONE48", "TWO24", "FOUR12" 
   )
   DSP48E1_inst (
      // Cascade: 30-bit (each) Cascade
      .ACOUT(ACOUT),                   // 30-bit A port cascade output
      .BCOUT(BCOUT),                   // 18-bit B port cascade output
      .CARRYCASCOUT(CARRYCASCOUT),     // 1-bit cascade carry output
      .MULTSIGNOUT(MULTSIGNOUT),       // 1-bit multiplier sign cascade output
      .PCOUT(PCOUT),                   // 48-bit cascade output
      // Control: 1-bit (each) Control
      .OVERFLOW(OVERFLOW),             // 1-bit overflow in add/acc output
      .PATTERNBDETECT(PATTERNBDETECT), // 1-bit active high pattern bar detect output
      .PATTERNDETECT(PATTERNDETECT),   // 1-bit active high pattern detect output
      .UNDERFLOW(UNDERFLOW),           // 1-bit active high underflow in add/acc output
      // Data: 4-bit (each) Data
      .CARRYOUT(CARRYOUT),             // 4-bit carry output
      .P(P),                           // 48-bit output
      // Cascade: 30-bit (each) Cascade
      .ACIN(ACIN),                     // 30-bit A cascade data input
      .BCIN(BCIN),                     // 18-bit B cascade input
      .CARRYCASCIN(CARRYCASCIN),       // 1-bit cascade carry input
      .MULTSIGNIN(MULTSIGNIN),         // 1-bit multiplier sign input
      .PCIN(PCIN),                     // 48-bit P cascade input
      // Control: 4-bit (each) Control
      .ALUMODE(ALUMODE),               // 4-bit ALU control input
      .CARRYINSEL(CARRYINSEL),         // 3-bit carry select input
      .CEINMODE(CEINMODE),             // 1-bit active high clock enable input for INMODE registers
      .CLK(CLK),                       // 1-bit Clock input
      .INMODE(INMODE),                 // 5-bit INMODE control input
      .OPMODE(OPMODE),                 // 7-bit operation mode input
      .RSTINMODE(RSTINMODE),           // 1-bit reset input for INMODE pipeline registers
      // Data: 30-bit (each) Data
      .A(A),                           // 30-bit A data input
      .B(B),                           // 18-bit B data input
      .C(C),                           // 48-bit C data input
      .CARRYIN(CARRYIN),               // 1-bit carry input signal
      .D(D),                           // 25-bit D data input
      // Reset/Clock Enable: 1-bit (each) Reset/Clock Enable
      .CEA1(CEA1),                     // 1-bit active high clock enable input for 1st stage A registers
      .CEA2(CEA2),                     // 1-bit active high clock enable input for 2nd stage A registers
      .CEAD(CEAD),                     // 1-bit active high clock enable input for pre-adder output registers
      .CEALUMODE(CEALUMODE),           // 1-bit active high clock enable input for ALUMODE registers
      .CEB1(CEB1),                     // 1-bit active high clock enable input for 1st stage B registers
      .CEB2(CEB2),                     // 1-bit active high clock enable input for 2nd stage B registers
      .CEC(CEC),                       // 1-bit active high clock enable input for C registers
      .CECARRYIN(CECARRYIN),           // 1-bit active high clock enable input for CARRYIN register
      .CECTRL(CECTRL),                 // 1-bit active high clock enable input for OPMODE and carry registers
      .CED(CED),                       // 1-bit active high clock enable input for D registers
      .CEM(CEM),                       // 1-bit active high clock enable input for multiplier registers
      .CEP(CEP),                       // 1-bit active high clock enable input for P registers
      .RSTA(RSTA),                     // 1-bit reset input for A pipeline registers
      .RSTALLCARRYIN(RSTALLCARRYIN),   // 1-bit reset input for carry pipeline registers
      .RSTALUMODE(RSTALUMODE),         // 1-bit reset input for ALUMODE pipeline registers
      .RSTB(RSTB),                     // 1-bit reset input for B pipeline registers
      .RSTC(RSTC),                     // 1-bit reset input for C pipeline registers
      .RSTCTRL(RSTCTRL),               // 1-bit reset input for OPMODE pipeline registers
      .RSTD(RSTD),                     // 1-bit reset input for D pipeline registers
      .RSTM(RSTM),                     // 1-bit reset input for multiplier registers
      .RSTP(RSTP)                      // 1-bit reset input for P pipeline registers
   );

   // End of DSP48E1_inst instantiation

 

If I use manual instantiation, should I add the synthesis on/off constructs? I know that these contructs are added to bypass code that you do not want to synthesize, but in this case, I am very very unsure...

 

Thank you.

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1 Reply
evgenis1
Advisor
Advisor
5,522 Views
Registered: ‎12-03-2007

Hi,

 

You didn't include the module declaration. It probably looks something like:

 

module my_module(  sclr, ce, clk, thresh0, q)   /* synthesis syn_black_box syn_noprune=1 */; 

 

input sclr;  input ce;  input clk;  output thresh0;  output [31 : 0] q;    // synthesis translate_off   

 

wire \BU2/U0/i_baseip.i_xbip_counter/i_thresh_detect.i_norm.i_gate/tier_gen[1].i_tier/loop_tiles[0].i_tile/lut_o<0> ; 

...other logic

 

// synthesis translate_on
endmodule

 

syn_black_box attribute tells synthesis tool that this module is a black box. After the synthesis, NGDBUILD will be looking for a netlist for this module, which is my_module.ngc. That's what CoreGen is generating.

 

The synthesis tool will ignore all the code between translate_on/off.

 

The code between translate_on/off is a simulation model of the my_module (simulators ignore translate_on/off)

 

If you manually instantiate DSP48E1 primitive, you do not use translate_on/off , because you want it to synthesize.

 

Thanks,

Evgeni

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