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Visitor paclopes
Visitor
776 Views
Registered: ‎03-01-2018

synthesizing BRAMs

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I wonted to ask for some more precise description to when VHDL ram signal is implemented as a BRAM.

 

I wrote some VHDL code (I am not very experienced) and all the RAMs came out distributed. Then I decided to make some experiments, that I present bellow, but experimenting should not be the way to go. My main conclusion it to use a BRAM component, but some times that results in harder to write and read code.

 

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity bram is
    Port (  
        output :    out STD_LOGIC;
        clock:  in std_logic
    );
end bram;

architecture Behavioral of bram is
    function to_vector(x:std_logic) return std_logic_vector is
        variable y: std_logic_vector(0 downto 0);
    begin
        y(0) := x;
        return y;
    end to_vector;

    signal addr: unsigned(9 downto 0) := (others => '0');
    signal rnd: unsigned(15 downto 0) := x"65a1";

    -- BRAM1: std_logic_vector
    subtype ram_type1 is std_logic_vector(1023 downto 0);
    signal RAM1: ram_type1;
    signal RAM1_out: std_logic;
    -- BRAM2: array of std_logic
    type ram_type2 is array (0 to 1023) of std_logic;
    signal RAM2: ram_type2;
    signal RAM2_out: std_logic;
    -- BRAM3: array of std_logic_vector
    type ram_type3 is array (0 to 1023) of std_logic_vector(0 downto 0);
    signal RAM3: ram_type3;
    signal RAM3_out: std_logic_vector(0 downto 0);
    -- BRAM4: array of std_logic_vector with a condition on the read
    type ram_type4 is array (0 to 1023) of std_logic_vector(0 downto 0);
    signal RAM4: ram_type4;
    signal RAM4_out: std_logic_vector(0 downto 0);
    -- BRAM5: array of std_logic_vector with logic before the output reg
    type ram_type5 is array (0 to 1023) of std_logic_vector(0 downto 0);
    signal RAM5: ram_type5;
    signal RAM5_out: std_logic_vector(0 downto 0);
    
    -- Inputs
    signal RAM_in0 : std_logic;
    signal RAM_in1 : std_logic_vector(0 downto 0);
begin
    process(clock)
    begin
        if rising_edge(clock) then
            addr <= addr + 1;
            -- Linear Feedback Shift Register
            rnd <= rnd(14 downto 0) & (rnd(10) xor rnd(12) xor rnd(13) xor rnd(15));
        end if;
    end process;
    
    output <= RAM2_out xor RAM2_out xor RAM3_out(0) xor RAM4_out(0) xor RAM5_out(0);
    
    process (clock)
    begin
        if rising_edge(clock) then
            -- removed
            RAM1(to_integer(addr)) <= RAM1_out xor rnd(0);
            RAM1_out <= RAM1(to_integer(addr));
            
            -- removed
            RAM2(to_integer(addr)) <= RAM2_out xor rnd(1);
            RAM2_out <= RAM2(to_integer(addr));

            -- Implemented as BRAM
            RAM3(to_integer(addr)) <= to_vector(RAM3_out(0) xor rnd(2));
            RAM3_out <= RAM3(to_integer(addr));
            
            -- Implemented as BRAM with two ports
            RAM4(to_integer(addr)) <= to_vector(RAM4_out(0)xor rnd(3));
            if addr = "11" & x"24" then
                RAM4_out <= RAM4(to_integer(addr));
            end if;
            
            -- Implemented as Distributed RAM
            RAM5(to_integer(addr)) <= to_vector(RAM5_out(0) xor rnd(4));
            RAM5_out <= not RAM5(to_integer(addr));
            
        end if;
    end process;

end Behavioral;

 

 

 

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Adventurer
Adventurer
1,099 Views
Registered: ‎11-13-2017

Re: synthesizing BRAMs

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3 Replies
Adventurer
Adventurer
1,100 Views
Registered: ‎11-13-2017

Re: synthesizing BRAMs

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740 Views
Registered: ‎01-22-2015

Re: synthesizing BRAMs

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@paclopes 

 

    ...when VHDL ram signal is implemented as a BRAM.

In general, ug901 should be your guide when trying to write code that synthesizes into a particular type of hardware.

 

Please note that BRAM is usually used for data that is organized as a two-dimensional array.

           

Starting on about page 114 of Xilinx document ug901, you will find examples of VHDL code that synthesize into BRAM.

 

A short way to force the use of BRAM for a two-dimensional array called mybram is shown by code below (also see ug901, pg55):

type ram_type is array (127 downto 0) of std_logic_vector(7 downto 0);
signal mybram : ram_type;

attribute ram_style : string;
attribute ram_style of mybram : signal is "block";

cheers,

Mark

 

 

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Visitor paclopes
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Registered: ‎03-01-2018

Re: synthesizing BRAMs

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Ok, thanks I will take a look at this links...

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