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Highlighted
5,190 Views
Registered: ‎12-29-2016

system verilog packages - synthesis

I am trying to synthesize a design that contains system verilog packages and vivado doesn't seem to like this. 

 

 

for the sake of simplicity i tried grabbing a simple system verilog  package of the net:

 

 

 

package definitions;

typedef enum bit [1:0]{ADD, SUB, MUL} opcodes_t;

typedef struct{
logic [31:0] a, b;
opcodes_t opcode;
} instruction_t;

function automatic [31:0] multiplier(input [31:0] a, b);
return a*b;
endfunction

function void fun( input [31:0] result );
$display("result = %d",result);
endfunction


endpackage

 

 

but even this gives errors when on the line that declares the package???

 

 

So my question is this: Does vivado allow you to use system verilog packages??

 

i am using Vivado 16.2

 

system_verilog_packages.PNG
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Guide
Guide
5,176 Views
Registered: ‎01-23-2009

Re: system verilog packages - synthesis

Vivado definitely supports packages - both for Synthesis and simulation.

 

Are you sure that you have the file type defined correctly. Normally it should recognize the .sv suffix as a SystemVerilog file, but you can be sure by selecting the file in the Sources window and looking at the Type field in the General tab in the Source File Properties window

 

Or you can use the Tcl command

 

get_property FILE_TYPE [get_files definition.sv]

 

It should be set to SystemVerilog (and not, say, Verilog).

 

Avrum

 

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Teacher
Teacher
5,175 Views
Registered: ‎03-31-2012

Re: system verilog packages - synthesis

@mreisterextron I have definitely implemented designs with systemverilog packages and they work well. Without seeing your full setup it's difficult to see what the problem is.

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Moderator
Moderator
5,058 Views
Registered: ‎07-21-2014

Re: system verilog packages - synthesis

@mreisterextron

 

As already mentioned in above posts, Vivado supports SystemVerilog packages and tool should be able to compile it.

Make sure there are no other definition/name conflicts coming for the mentioned package. Also, can you share these SystemVerilog files for us to reproduce the same at our end?

 

Thanks,
Anusheel
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