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Adventurer
Adventurer
352 Views
Registered: ‎01-14-2008

systemverilog coding style

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Hi,

I'm new to verilog and I have a question, please see code below. I believe this code is perfectly fine.

always_ff @(posedge clk)
begin
   if (a) z <= 0;
   if (b) z <= 1;
end

However a college of mine claims that this problematic coding style which will lead to race conditions once synthesized. He claims the correct way for coding this is as such:

always_ff @(posedge clk)
begin
   if (b) z <= 1;
   else if (a) z <= 0;
end

I claim that both code snippets are exactly the same and make no difference in synthesis.

But since I'm new to verilog am not certain if this is true. Could somebody shed some light on this? Is the first coding style (without the else) correct. Or should this be avoided because of the danger of race conditions?

 

 

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Guide
Guide
309 Views
Registered: ‎01-23-2009

Re: systemverilog coding style

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If statement should always be used with else part defined in RTL.

“If” statements without an “else” branch can lead to undesired latch inference.

One has to be careful with a statement like this - this is only true in a combinatorial process - an always_comb or an always @(*). In an always_ff or an always @(posedge clk) this result in a flip-flop with an enable, which is not only legal, but preferred when possible (since proper use of the chip-enable can reduce power).

So the two pieces of code will result in the same behavior, both in simulation and in synthesis. Both are legal.

If you want to see this, it is easy to elaborate both these pieces of code and see the generic technology result - it should be easy to see that they synthesize to the same logic.

Avrum

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Xilinx Employee
Xilinx Employee
341 Views
Registered: ‎05-22-2018

Re: systemverilog coding style

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Hi @dsula ,

If statement should always be used with else part defined in RTL.

“If” statements without an “else” branch can lead to undesired latch inference.

Thanks,

Raj

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Adventurer
Adventurer
331 Views
Registered: ‎01-14-2008

Re: systemverilog coding style

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@rshekhaw 

 

 

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Guide
Guide
310 Views
Registered: ‎01-23-2009

Re: systemverilog coding style

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If statement should always be used with else part defined in RTL.

“If” statements without an “else” branch can lead to undesired latch inference.

One has to be careful with a statement like this - this is only true in a combinatorial process - an always_comb or an always @(*). In an always_ff or an always @(posedge clk) this result in a flip-flop with an enable, which is not only legal, but preferred when possible (since proper use of the chip-enable can reduce power).

So the two pieces of code will result in the same behavior, both in simulation and in synthesis. Both are legal.

If you want to see this, it is easy to elaborate both these pieces of code and see the generic technology result - it should be easy to see that they synthesize to the same logic.

Avrum

View solution in original post