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Observer
Observer
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Registered: ‎07-16-2018

systemverilog getenv dpi

Hello,

Is it possible to use an environment variable as a string in a synthesis script?

I'm trying to use something like

import "DPI-C" function string getenv(input string env_name);

followed by a call to

{getenv("ROMDIR"), "/fft/s0_re.hex" }

However, vivado complains about the string variable type, which apparently isn't supported, so I've modified the original definition to

import "DPI-C" function reg[1023:0] getenv(input reg[1023:0] env_name);

But this doesn't work either (the getenv("ROMDIR") part just evaluates to nothing and so it looks for the "/fft/s0_re.hex" file relative to root.

I need this capability because I use the verilog module from different directories (synthesis called from one directory, tests from another). The only solution I can find so far that works is to use an absolute path, but then anyone who uses this code must modify the file paths. How can I do this? Thanks.

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Moderator
Moderator
558 Views
Registered: ‎07-21-2014

@matthuszagh 

In case if you are trying to edit the RTL file using the hook(tcl) scripts, then this is something which is not supported with the Synthesis tool yet.

Thanks
Anusheel

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Observer
Observer
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Registered: ‎07-16-2018

@anusheelthanks for the reply. So to be completely explicit, there's no way to do what I'm trying to do with xilinx/systemverilog?

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Moderator
Moderator
503 Views
Registered: ‎07-21-2014

@matthuszagh 

Yes, as of now you need to modify the RTL using script outside of Vivado environment and then invoke the tool with a modified version of the RTL.

Thanks
Anusheel 

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