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Registered: ‎06-27-2019

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Xilinx Employee
Xilinx Employee
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Registered: ‎05-22-2018

Hi wisefuture0@gmail.com ,

Post-Synthesis timing simulation uses the estimated timing delay from the device models. So, you might me seeing multiple clock cycle delays for output.

Please check the below post:

https://forums.xilinx.com/t5/Simulation-and-Verification/Vivado-Post-synthesis-simulation/td-p/833937

Thanks,

Raj

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