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use posedge and negedge clk to drive the same register, is it possible?

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Newbie
Posts: 4
Registered: ‎04-16-2017
Accepted Solution

use posedge and negedge clk to drive the same register, is it possible?

I am trying to drive the same register (current_state) using both posedge and negedge clk. Are there any sample codes for this purpose?

 

The following is what I am trying to do, but the same register can't appear in two always blocks:

 

always @(posedge clk) begin
    if (!reset) begin
        current_state <= step0;
    end
end // end of always for reset signal

// set up proper en and en_product&wr_product @(negedge clk)
always @(negedge clk) begin
    if (reset)
        current_state <= next_state;
end // end of always for non-reset signal

 

Thanks in advance!

 

 


Accepted Solutions
Highlighted
Teacher
Posts: 4,979
Registered: ‎03-31-2012

Re: use posedge and negedge clk to drive the same register, is it possible?

@cindyzhang20096 most registers in Xilinx FPGAs (except the DDR registers in the IO cells) can only support a single edge of the clock. What you want is not generally doable for regular logic. I'd suggest running your system at 2x speed and using only one edge of the clock. This will require timing the system at exactly the same period ie with both edges, you need to time your system at half-period of either clock (and manage the skew between to edges) which is the period of the 2x clock so timing challenge doesn't get worse.

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Adventurer
Posts: 59
Registered: ‎04-12-2017

Re: use posedge and negedge clk to drive the same register, is it possible?

In an FPGA you don't use posedge and negedge, at least in all the designs I have seen it is never used. It is a nightmare when analyzing the timing because the negedge is another clock.

 

You'd better stick to posedge logic for all your FFs unless you have an excellent reason to do otherwise (and in all my experience I have never seen a good reason to do such a thing, but I can always be proven wrong).

Avi Chami MSc
FPGA Site
Highlighted
Teacher
Posts: 4,979
Registered: ‎03-31-2012

Re: use posedge and negedge clk to drive the same register, is it possible?

@cindyzhang20096 most registers in Xilinx FPGAs (except the DDR registers in the IO cells) can only support a single edge of the clock. What you want is not generally doable for regular logic. I'd suggest running your system at 2x speed and using only one edge of the clock. This will require timing the system at exactly the same period ie with both edges, you need to time your system at half-period of either clock (and manage the skew between to edges) which is the period of the 2x clock so timing challenge doesn't get worse.

- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.