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mm_uzair
Adventurer
Adventurer
6,440 Views
Registered: ‎11-17-2009

using DCM in virtex-5

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i am a bit new user to FPGA, i have a problem in generating 450MHz clock through the use of DCM, i am using  virtex-5 FPGA LX50T.

 

Here is a sample code i am trying all four type of DCM, but still same problem

------------------------------------------------------------------------------------------------------------------------------------------------------------

module checkk(clk,rst,clk_final,CLKIN_IBUFG_OUT,locked);  
input clk;
input rst;
output clk_final;
output CLKIN_IBUFG_OUT;
output locked;
// Instantiate the DCM module
dcmm instance_name (
    .CLKIN_IN(clk),
    .RST_IN(rst),
    .CLKIN_IBUFG_OUT(CLKIN_IBUFG_OUT),
    .CLKOUT0_OUT(clk_final),
    .LOCKED_OUT(locked)
    );
wire [35:0] ILAControl;
icon i_icon(.CONTROL0(ILAControl));
ila i_ila(.CONTROL(ILAControl), .CLK(clk_final), .TRIG0(clk_final) );

endmodule

----------------------------------------------------------------------------------------------------------------------------------------

 

I am facing a problem  when i assign clk to global clock pin through user constraints, error is there that pin is driving non iobuf pin, when i search that option on xilinx,it says turn off automatic iobuf insertion option, i have done that but still place are route does not complete, althogh no error is displayed, the logs for "place & route" are attached in attached file,some importants warnings are

 

-----------------------------------------------------------------------------------------------------------------------------------------

 WARNING:Par:288 - The signal i_ila_2/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_data<8> has no load.
   PAR will not attempt to route this signal.

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish
   the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement
   or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list
   of (up to 10) such unroutable connections:
     Unroutable      signal: dcm12_1/CLKOUTDCM0_CLKIN      pin:  dcm12_1/FD2_Q_OUT/CLK
     Unroutable      signal: dcm12_1/CLKOUTDCM0_CLKIN      pin:  dcm12_1/FD1_Q_OUT/CLK
     Unroutable      signal: dcm12_1/CLKOUTDCM0_CLKIN      pin:  dcm12_1/FD3_Q_OUT/CLK
     Unroutable      signal: dcm12_1/CLKOUTDCM0_CLKIN      pin:  dcm12_1/FDS_Q_OUT/CLK

 -----------------------------------------------------------------------------------------------------------------------------------------

 Now i need your help, how to give proper clock input to DCM??  and which type of DCM to use?? i will be very very greatfull if you explain this

specially with some example

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Accepted Solutions
blaine
Xilinx Employee
Xilinx Employee
7,591 Views
Registered: ‎04-11-2008

MM,

 

Firstly I would use a PLL to generate a clock with a frequency of 450MHz. The jitter performance will be better.

Secondly, Chipscope will not run that quick.

 

Regarding the connections you need to:

i) Lock your input to a GCLk pin. In your toplevel code something like NET "clk" LOC = XXXX;

ii) Have a connection PAD -> IBUF(G) -> PLL/DCM for an external clock. You are not allow loads other than a single IBUF between the pad and IBUF.

iii) Internal connections are allowed but they must go through a BUFG to get to an input of a PLL.

 

I think you have an IBUF inside the architecture wizard. You are also connecting the input clk to other loads. If you want to do this then you need to connect to CLKIN_IBUFG_OUT.

 

JB

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4 Replies
nyashwanth
Visitor
Visitor
6,439 Views
Registered: ‎11-03-2009

In the synthesis options, is the "Add IO buffers" option selected??

It should be selected.

 

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mm_uzair
Adventurer
Adventurer
6,444 Views
Registered: ‎11-17-2009

no it is not selected, when i select this error comes during synthesis saying that clk has dual connection (ie.it is connected to H17(global clock) and also to the input of dcm. i am using type DCM to PLL v9.1 in virtex-5 clocking but similar problem exits when i use other type of dcm

 

 

regards,

uzair

dcmm.JPG
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blaine
Xilinx Employee
Xilinx Employee
7,592 Views
Registered: ‎04-11-2008

MM,

 

Firstly I would use a PLL to generate a clock with a frequency of 450MHz. The jitter performance will be better.

Secondly, Chipscope will not run that quick.

 

Regarding the connections you need to:

i) Lock your input to a GCLk pin. In your toplevel code something like NET "clk" LOC = XXXX;

ii) Have a connection PAD -> IBUF(G) -> PLL/DCM for an external clock. You are not allow loads other than a single IBUF between the pad and IBUF.

iii) Internal connections are allowed but they must go through a BUFG to get to an input of a PLL.

 

I think you have an IBUF inside the architecture wizard. You are also connecting the input clk to other loads. If you want to do this then you need to connect to CLKIN_IBUFG_OUT.

 

JB

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ywu
Xilinx Employee
Xilinx Employee
6,391 Views
Registered: ‎11-28-2007

Please see http://forums.xilinx.com/xlnx/board/message?board.id=IMPBD&message.id=924#M924

 

mm_uzair: this is exactly why you shouldn't ask the same question in more than one board. Other people may be wasting time answering the same question that may have already been resolved.

 

Cheers,

Jim

Cheers,
Jim
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