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Contributor
Contributor
331 Views
Registered: ‎06-17-2016

using register

Hi

I studied "UG949" and it mentioned that registers help to decrease fanout and "place and route" tools.

I investigated some Xilinx IP schematic and there were registers in input and outputs pin.

Consequently, I decided to set register in all input and output pin of components(except clock pin) in VHDL programming as a methodology.

Q1:

Is it true to set register in all input and output pin of components(except clock pin) in VHDL programming as a methodology?

 

Q2:

If the answer is "NO", Please, explain which pins need to be registered?

 

In some Xilinx documents mention that we should enable"internal pipeline registers in DSP48" or "output register for BRAM".

Q3: 

Please, explain how I can enables the registers above?

 

Best Regards

 

 

 

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6 Replies
Explorer
Explorer
325 Views
Registered: ‎03-17-2011

Re: using register

Hi @dariush84

Q1: yes this is a good practise.

Q3: Two ways I can think of:

a. if you're using the IPI, you can configure the IP block (BRAM or DSP) to register the output.

b. if you're instanciating the IP in HDL code, it should be a generic parameter to set.

 

--Sebastien
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Contributor
Contributor
278 Views
Registered: ‎06-17-2016

Re: using register

Hi

Can you explain about "Q1" more?

 

BR

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260 Views
Registered: ‎01-22-2015

Re: using register

@dariush84

Q1: Is it true to set register in all input and output pin of components(except clock pin) in VHDL programming as a methodology?

Using VHDL we design “clocked logic” digital circuits that are to be implemented inside the FPGA. In short, clocked-logic circuits are constructed from clocked-components called registers (also called flip-flops) and unclocked-components called combinational logic (eg. AND-gates, OR-gates). As the names imply, clocked-components have a clock-input pin and unclocked-components do not. The basic operation of clocked-logic is that a clock edge (lets call it EDGE1) causes a digital signal input (lets call it SIGA) of a register (lets called it REGA) to be passed to the output of REGA. SIGA then travels through combinational logic which creates a new digital signal (lets call it SIGB). SIGB eventually reaches another register (lets call it REGB). On the clock edge following EDGE1 (lets called it EDGE2), SIGB is captured by REGB and passed to the output of REGB.

That is, the clocked-logic sequence of events is:

  1. clock EDGE1 launches SIGA from the output of REGA 
  2. SIGA travels through combinational logic (and wires) where it becomes SIGB and eventually reaches REGB
  3. clock EDGE2 captures SIGB at REGB, passing it to output of REGB

This orderly passing of SIGA from one register to the next gives SIGA plenty of time to complete its journey through the combinational logic and become SIGB. As SIGA travels through the combinational logic, it can be combined with other signals via digital operations (eg. AND, OR). These other signals might have traveled farther than SIGA to reach the combinational logic. The different arrival times for SIGA and the other signals at the combinational logic can cause the output of the combinational logic to toggle for a short while before settling at the correct value. This toggling of the combinational logic output is called glitches. However, if we wait long enough before using the output of the combinational logic then we can avoid the glitches and get only the correct value. This is the purpose of the clock in clocked-logic. That is, when the clock has a long-enough period, then REGB will capture only the correct value from the combinational logic (and not the glitches).  

The FPGA tools (eg. Xilinx Vivado) do timing analysis to check that the passing of signals from one register to the next is done in a way that avoids the capture of glitches. If timing analysis finds a problem, then it will tell you. Then, you must somehow change your design to avoid the problem (eg. use a clock with a longer period).

Finally, we come to your question. If your design “looks at” the output of the combinational logic then your design will see the glitches. However, if your design “looks at” the output of a register (eg. REGB) then you will see the correct value of the digital signals (and not the glitches).  So, for example, if you are sending a digital signal out of the FPGA then you should send it from the output of a register and NOT from the output of combinational logic - otherwise you could be sending glitches out of the FPGA.

Cheers,
Mark

217 Views
Registered: ‎01-22-2015

Re: using register

@dariush84

Q1: Is it true to set register in all input and output pin of components(except clock pin) in VHDL programming as a methodology?

Today, I find that my response of yesterday only answered part of your question.

Yesterday I said that signal outputs of the FPGA should be sent through a register and then directly to the output-pin of the FPGA. However, you also asked about signals that are inputs to the FPGA….

In short, signals that are inputs to the FPGA are usually sent from the input-pin immediately to a register, which “captures the signal”.  This makes sense because signal inputs must enter the “clocked logic” of the FPGA in order to be processed by the FPGA. However, it is important to ask, “ What clock should be used for the register that captures the signal input? ”.

Ideally, a signal coming into the FPGA has been launched from a register located outside the FPGA. When this is true, then the clock used on the external register should also be the clock used on the register inside the FPGA that captures the signal. Devices such as digitizers (ADCs) often send a clock (called a data-clock) along with the data that they produce. Thus, for external ADCs, we often use the data-clock to clock the FPGA register(s) that capture the ADC data.

However, sometimes a signal coming into the FPGA was not launched by a register located outside the FPGA.  An example of this is a person who pushes a switch which creates an ON/OFF signal that is sent to the FPGA. These types of signals are called asynchronous (async for short) inputs to the FPGA. Since no clock was involved with creation of the signal then we are free to use an FPGA internal clock on the register that captures the async signal. However, with async inputs, there is a chance that the input could change almost simultaneously with the edge of the FPGA clock used on the capture register. When this happens, the capture register can become unstable – a condition that is called register metastability. To fight the metastability problem, we use VHDL to create back-to-back-register circuits called synchronizers that can be used to safely capture the async input.

I know you are just learning VHDL – and I have thrown a lot of stuff at you. So, for now, just put a register on every input and output of the FPGA - and focus on writing functionally correct VHDL. Learning and using Vivado simulation will tell you whether your VHDL is functionally correct. Later, we can talk more about metastability, synchronizers, and timing analysis.

Cheers,
Mark

Contributor
Contributor
195 Views
Registered: ‎06-17-2016

Re: using register

Hi

Thank you so much for your explanations

I conclude that I must use registers for input and output port of FPGA  and I  should use registers in I/O pin of 

components in the FPGA when there are some problems like metastability or glitches but not for every component that is writing in VHDL.

Now, I'm writing VHDL code and I simulate the code in behavioral mode and investigate it in RTL elaboration.

 

Best Regards

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Scholar drjohnsmith
Scholar
185 Views
Registered: ‎07-09-2009

Re: using register

Yes to all the other arguments, and..
In practice, FPGAs are register rich, logic / routing delay poor. lots of registers in the design make routing / speed optimising easy at effectively zero over head , different to ASICs.
Also
When designing modules / units to be re used, If you have registers on front and back, then you have a design / timing that can be reproduced. If you have say the output as a combinational output, then the output could be twice the delay of the clock to clock of the block, and you might not notice, till you tried to integrate it with other blocks.
Like all 'rules' there are times to break the register in / out rule, but thats experience.