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Registered: ‎03-03-2017

verilog Top module conditional module inputs

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I am working on a project in Vivado 2019.1 where I am running 3 separate synthesis/implementation runs for the same set of verilog files with each synth/impl setup for a different device (Artix 7 35T, 75T, 100T).   For the 100T I need to add a small amount of additional circuitry including additional input/output pins in the Top module.   I know I can use a generate block with parameter definitions defined in the Synth run settings "More Options", which I am already utilizing.   My question is how to I use either generate, or ifdef to have additional input/output pins for one of the device synth/impl runs (without having to use separate top module files).

Thanks.

Tim

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Registered: ‎05-16-2018

Re: verilog Top module conditional module inputs

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Hi Tim,

Check out AR #51164

Add synthesis option "-verilog_define MACRO_NAME=MACRO_VALUE".

Eric

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Registered: ‎05-16-2018

Re: verilog Top module conditional module inputs

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Hi Tim,

This should be doable with ifdefs.  Use the ifdefs around the IO in your top level module and define or don't define the ifdef in More Options.  The second part you need is to have different IO constraints for different builds so that all your IOs are placed properly in the 100T and you don't get errors for having constraints for IOs that don't exist in the other implementations.   I suggest you put the IO constraints for the 100T only IOs in a separate .xdc file and only include that constraint file in the constraint set for the 100T.

Eric

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Registered: ‎03-03-2017

Re: verilog Top module conditional module inputs

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@sarman_1998 ,

   Thanks for the quick reply.   To confirm I do already use a separate constraint file for the 100T synth/impl run.    I didn't realize you could do defines in the More Options section.   Do you possibly have an example of the syntax required for this?

Thanks.  
Tim

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Registered: ‎05-16-2018

Re: verilog Top module conditional module inputs

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Hi Tim,

Check out AR #51164

Add synthesis option "-verilog_define MACRO_NAME=MACRO_VALUE".

Eric

View solution in original post