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s002wjhw
Voyager
Voyager
1,658 Views
Registered: ‎06-26-2015

verilog function error ise

ise give these error any idea? line 1 expecting 'EOF', found 'function'

here is the code

function integer log2;
input integer value;
for (log2=0; value>0; log2=log2+1)
value = value >> 1;
endfunction

10 Replies
markcurry
Scholar
Scholar
1,642 Views
Registered: ‎09-16-2009

Post more context.

In Verilog-2001 (which is all ISE supports) functions may only be defined within a module scope.  I'm guessing your function is not defined within a module.

Regards,

Mark

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viviany
Xilinx Employee
Xilinx Employee
1,610 Views
Registered: ‎05-14-2008

It is hard to know why with only a code snippet. 

Can you attach the whole file?

-vivian

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s002wjhw
Voyager
Voyager
1,579 Views
Registered: ‎06-26-2015

that is the whole code, i'm guessing because it doesn't have module.

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s002wjhw
Voyager
Voyager
1,570 Views
Registered: ‎06-26-2015

the error was cause by not adding the module. however after i add module i got this error
line 15 External function may not be used in a constant expression
this is a code called log2.v
module log2();
function integer log2;
input integer value;
for (log2=0; value>0; log2=log2+1)
value = value >> 1;
endfunction
endmodule

another verilog file call the function

module cic_decim
#(
parameter DATAIN_WIDTH = 16,
parameter DATAOUT_WIDTH = DATAIN_WIDTH,
parameter M = 2,
parameter N = 5,
parameter MAXRATE = 64,
parameter bitgrowth = N*log2(M*MAXRATE)
)
(
input clk_i,
input rst_i,
input en_i,
input [DATAIN_WIDTH-1:0] data_i,
output [DATAOUT_WIDTH-1:0] data_o,
input act_i,
input act_out_i,
output val_o
);
parameter bitgrowth = N*log2(M*MAXRATE) output the error. not sure whats wrong with it.

markcurry
Scholar
Scholar
1,566 Views
Registered: ‎09-16-2009

In ISE you cannot call a function call defined within one module from another module.

To solve this in ISE, stick the function defintion in an include file, and `include it in BOTH modules.

To solve this clean, using SystemVerilog (which requires Vivado) one would place the single defintion in a package.

Regards,

Mark

s002wjhw
Voyager
Voyager
1,549 Views
Registered: ‎06-26-2015

i did put 'include "log2.v" before module that use log2 function, but still getting the error.  the log2.v was indicated as included file under ISE

so it look like this, but getting same error

'include "log2.v"

module cic_decim

#(

parameter grow=N*log2(M*MX)

)

vineeshvs
Observer
Observer
1,109 Views
Registered: ‎11-26-2018

Facing the same issue with Verilog-2001. Please post an answer where I can have a function defined in a Verilog file, include it in another module and get it work. I want to avoid the scenario where same function needs to be copy-pasted in all modules.

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markcurry
Scholar
Scholar
1,063 Views
Registered: ‎09-16-2009

Simply put the `include within the module defintion:

module cic_decim
#(
  parameter grow=N*log2(M*MX)
)();
  'include "log2.v"
endmodule

This sort of "forward" deceleration is allowed in Verilog-2001 for ANSI-C style portlists.  For Verilog-2001 functions must be defined within a module scope. One cannot, as the above thread attempted, to define a a function at global scope.

Regards,

Mark

viviany
Xilinx Employee
Xilinx Employee
1,031 Views
Registered: ‎05-14-2008

Start a new post for your question please.

Do you have the same error?

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
vineeshvs
Observer
Observer
1,023 Views
Registered: ‎11-26-2018

[Fix/workaround] I was compiling the .v file which did not have a module but had only functions. I was compiling those files also using the vlog command in Modelsim. That was the reason for the error. When I stopped compiling them, the error vanished.

Note: These files with only function definitions were included (using `include) in other files inside modules. It is okay with Verilog-2001. I did not have to compile the .v files with only function definitions in the first place.