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Voyager
Voyager
1,120 Views
Registered: ‎10-12-2016

veriolg protected code read error during synthesis in vivado ?

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Hi Friends,

 

I have verilog design file in that i have some part of code in between `protect and `endprotect. when compiler parses this it was throwing error.  How to solve this. 

 

NOTE: Any help or suggestions are highly appreciated.

 

Thank you 

S Sampath 

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Voyager
Voyager
1,271 Views
Registered: ‎10-12-2016

Re: veriolg protected code read error during synthesis in vivado ?

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Hi The same protected RTL files are synthesized in the 2015.4 version but not in 2016.4. Currently am proceeding with 2015.4 version. 

 

 

Thank You 

S Sampath 

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Scholar watari
Scholar
1,090 Views
Registered: ‎06-16-2013

Re: veriolg protected code read error during synthesis in vivado ?

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Hi @ssampath

 

First of all, how do you or someone encrypt verilog design file ?

Vivado can only recognize encrypted verilog files by Vivado.

If your encrypted file is generated by Cadence and Synopsys's tools, Vivado can not recognize it.

 

If your encrypted file is generated by Vivado, generally, like this bug is related to "port connection" or "port definition".

So, would you make sure port connection or port definition with related document file ?

 

Best regards,

 

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Voyager
Voyager
1,272 Views
Registered: ‎10-12-2016

Re: veriolg protected code read error during synthesis in vivado ?

Jump to solution

Hi The same protected RTL files are synthesized in the 2015.4 version but not in 2016.4. Currently am proceeding with 2015.4 version. 

 

 

Thank You 

S Sampath 

0 Kudos