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16,449 Views
Registered: ‎06-17-2013

vhdl-93 in vivado

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Does anybody know how to set the vhdl-93 option in Vivado 2013.1 ?

In ISE, there was the possibility to set the "VHDL Source Analysis Standard" property to "VHDL-93".

In Vivado, I didn't find any way to set this option.

Unfortunately ISE is not an option because I have a gated clock design, which I need to translate with
the "gated_clock_conversion" option, which is only available in Vivado.

 

So does anybody know how to set the vhdl-93 option in Vivado ?

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Visitor dak_zach
Visitor
18,325 Views
Registered: ‎06-21-2013

Re: vhdl-93 in vivado

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I got my problem figured out, hopefully it's the same problem that andre.bischof had.  I probably should have noticed it sooner, but it all makes sense now.  I have been writing in VHDL, but I am calling a Verilog module (a file from an IPCore) and Vivado does not yet support mixed-language direct instantiation (http://www.xilinx.com/support/answers/47454.htm).  The answer record basically tells you that you have to declare the Verilog component in VHDL.

 

The answer record also says that they will revisit this types of mixed-language issues if there are enough requests in the future.

 

I still have my Webcase open, and am asking which version of VHDL Vivado uses since I can't find it listed anywhere.  I'll post the answer if I get anything back.

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34 Replies
Xilinx Employee
Xilinx Employee
16,446 Views
Registered: ‎05-14-2008

Re: vhdl-93 in vivado

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Do you encounter any problem synthesizing your VHDL code?

 

Vivian

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16,440 Views
Registered: ‎06-17-2013

Re: vhdl-93 in vivado

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Yes I got problems with the instantiation of components, for example:

 

  i_addsub_to_flat : entity dware_lib.addsub
    generic map (width => 3*(half_width+2)+half_width)
    port map (
      a       => l51_addsub_a_interleaved,
      b       => l51_addsub_b_interleaved,
      ci      => l51_addsub_ci_ll,
      add_sub => '0',
      sum     => l51_addsub_sum_interleaved,
      co      => l51_addsub_co_uu
      );

 

Vivado complains about using the constant '0' in the port map,

and the instantiatin without component declaration (both marked red).

Both are vhdl-93 features, which is no problem in ISE, but gives errors in Vivado.

 

I have to map a huge design on the FPGA so modifying all code to vhdl-87 style is not an option.

 

 

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Xilinx Employee
Xilinx Employee
16,435 Views
Registered: ‎05-14-2008

Re: vhdl-93 in vivado

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I'll check this and get back to you.

 

Vivian

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Xilinx Employee
Xilinx Employee
16,431 Views
Registered: ‎05-14-2008

Re: vhdl-93 in vivado

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Can you post the error messages from Vivado?

 

Vivian

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16,424 Views
Registered: ‎06-17-2013

Re: vhdl-93 in vivado

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for using a constant '0' in the port map, I get the error message:

 

[Synth 8-2396] near character '0'; 3 visible types match here

 

 

 

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16,416 Views
Registered: ‎06-17-2013

Re: vhdl-93 in vivado

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for instantiating without component declaration, I get the error message:

 

[Synth 8-493] no such design unit xxxxxxxxx

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16,390 Views
Registered: ‎06-17-2013

Re: vhdl-93 in vivado

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Please find a simple test case attached.

 

In test87.vhd, component instantiation and port mapping are done in vhdl-87 style.

This code synthesized without any errors.

In test93.vhd, component instantiation and port mapping are done in vhdl-93 style.

There are the following errors:

 

ERROR: [Synth 8-2396] near character '0' ; 3 visible types match here
ERROR: [Synth 8-493] no such design unit: blk

 

Are you really sure that Vivado supports VHDL-93 by default ?

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Historian
Historian
16,377 Views
Registered: ‎02-25-2008

Re: vhdl-93 in vivado

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andre.bischof wrote:

 

Are you really sure that Vivado supports VHDL-93 by default ?


Hopefully it supports by default a version that's a lot less ancient than VHDL'93! It is, after all, 2013. it should do VHDL-2008. Read the synthesis guide to be sure.

----------------------------Yes, I do this for a living.
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16,364 Views
Registered: ‎06-17-2013

Re: vhdl-93 in vivado

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Please take your time and try to synthesize the simple expample code I attached to my previous post,

and you will see that Vivado cannot handle the VHDL-93 example.

It surprises me that ISE can handle it, but not Vivado ...

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Visitor dak_zach
Visitor
14,967 Views
Registered: ‎06-21-2013

Re: vhdl-93 in vivado

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I am also experiencing the same problem.

 

When I put a constant in the port map, I get the error:

[Synth 8-2396] near character '0'

 

With a signal in the port map is assigned a constant, I get the error:

[Synth 8-493] no such design unit XXXX

 

It basically looks the same as in andre.bischof's test file.  It would be helpful if anyone could answer if there is an option to choose which VHDL version is being used.  All of the code that I've written is in VHDL-93, so changing it all over for Vivado is not an option.

 

 

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Scholar brimdavis
Scholar
14,928 Views
Registered: ‎04-26-2012

Re: vhdl-93 in vivado

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>

>Are you really sure that Vivado supports VHDL-93 by default ?

>

I think what you are wrestling with is a library issue, not a language version issue.

The port errors are just a red herring caused when Vivado can't find the entity.

 

>

> i_addsub_to_flat : entity dware_lib.addsub

>

How are you telling Vivado to find your 'dware_lib'  ?

 

>

>Please find a simple test case attached.

>

Your simple test case is missing the necessary library information needed for direct instantiation.

Either add a 'use work.blk' at the top, or change the instantiation to 'work.blk' instead of just 'blk'

 

It then will compile with Vivado 2013.2

 

-Brian

Visitor dak_zach
Visitor
14,896 Views
Registered: ‎06-21-2013

Re: vhdl-93 in vivado

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I've been fighting this problem for a couple days now and just finally got through synthesis without any errors or critical warnings related to this problem (just updated to 2013.2, but that didn't help with this error).

 

It seemed like the compiler didn't know about the design I was trying to instantiate, but it was showing up in the hierarchy.  Vivado originally had the "Hierarchy Update" set to "Automatic Update, Manual Compile Order", so maybe it was compiling my top level before any of the lower levels, but setting it to Automatic Update and Compile Order didn't change anything.

 

I eventually got it to synthesis by declaring my components rather than instantiating with the entity library. 

 

instead of:

uut : entity work.test
port map(
in1 => signal1,
out1 => signal2
);

 

use:

component test is
port(
in1 : in std_logic;
out1 : out std_logic
);
end component test;

begin

uut : test
port map(
in1 => signal1,
out1 => signal2
);

end;

 

 

Correct me if I'm wrong, but VHDL-93 added in the functionality to instantiate based on the library rather than declaring the component.  From that, it seems like Vivado is using VHDL-87.  I couldn't find anything in the synthesis guide about which version of VHDL is being used.  VHDL-2008 was suppose to be supported in 2013, but got moved back to 2014 (http://www.xilinx.com/support/answers/51502.html).  You would think they would support other versions like 93 or 2002 before going to 2008.  If anyone actually knows what version of VHDL Vivado uses or if it can be changed, it would be really helpful to know.

 

 

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Historian
Historian
14,889 Views
Registered: ‎02-25-2008

Re: vhdl-93 in vivado

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@dak_zach wrote:

I've been fighting this problem for a couple days now and just finally got through synthesis without any errors or critical warnings related to this problem (just updated to 2013.2, but that didn't help with this error).

 

It seemed like the compiler didn't know about the design I was trying to instantiate, but it was showing up in the hierarchy.  Vivado originally had the "Hierarchy Update" set to "Automatic Update, Manual Compile Order", so maybe it was compiling my top level before any of the lower levels, but setting it to Automatic Update and Compile Order didn't change anything.

 

I eventually got it to synthesis by declaring my components rather than instantiating with the entity library. 

 


Well, that's totally fscking borked that a synthesis tool in 2013 cannot deal with direct instantiations.

 

File a WebCase and let's see what Xilinx has to say about it.

----------------------------Yes, I do this for a living.
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Historian
Historian
14,888 Views
Registered: ‎02-25-2008

Re: vhdl-93 in vivado

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Having said that, it does seem like it's an order-of-compilation issue, and if the tools can't figure out the hierarchy then they're borked because this has been working in ISE since basically forever.

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
14,873 Views
Registered: ‎05-14-2008

Re: vhdl-93 in vivado

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Does it help if you set test.vhd as global included by right-clicking the file?

 

Vivian

 

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Visitor dak_zach
Visitor
14,857 Views
Registered: ‎06-21-2013

Re: vhdl-93 in vivado

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I had tried setting the file to a global include before, and I got the same errors.

 

One thing I did omit from a previous post was the whole error message, but andre.bischof included the whole thing:

 

[Synth 8-2396] near character '0'; 3 visible types match here

 

It seems like since it hasn't compiled the file and therefore doesn't know the inputs/outputs, it is trying to decide if the constant '0' is a std_logic, std_ulogic, or a bit.  That would align with what I'm thinking, that it is either a VHDL-93 problem, or a compilation order problem.

 

I'll open up a webcase and see if we can get anywhere on it.

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Xilinx Employee
Xilinx Employee
14,826 Views
Registered: ‎05-14-2008

Re: vhdl-93 in vivado

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It'll be helpful for others if you can post the final conclusion of this issue from the Webcase in this thread. Thanks.

 

Vivian

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14,808 Views
Registered: ‎06-17-2013

Re: vhdl-93 in vivado

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I agree it really looks like a  compilation-order problem.

 

With the simple test case (test.vhd), I tried the following:

 

* After setting "automatic compilation order", I checked the "compile order" tab.
  The order looks ok: sub block first, then the top block.

  However, I get the error messages mentioned before.

 

* After setting "manual compilation order", I manually specified the compilation order:

  sub block first, then the top block.,

  I still get the same error messages.

 

I guess if it was a compilation order problem, it would have been resolved by manually setting the correct order ...

 

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Scholar brimdavis
Scholar
14,792 Views
Registered: ‎04-26-2012

Re: vhdl-93 in vivado

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Andre wrote:

>
> I agree it really looks like a  compilation-order problem.

>

Please see my post of 06-26-2013

 

I tried your test93.vhd example in 2013.2; once the missing library information is provided for the direct instantiation, it compiles successfully.

 

I also tried several other small designs using direct instantiation with no issues seen.

 

-Brian

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Visitor dak_zach
Visitor
18,326 Views
Registered: ‎06-21-2013

Re: vhdl-93 in vivado

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I got my problem figured out, hopefully it's the same problem that andre.bischof had.  I probably should have noticed it sooner, but it all makes sense now.  I have been writing in VHDL, but I am calling a Verilog module (a file from an IPCore) and Vivado does not yet support mixed-language direct instantiation (http://www.xilinx.com/support/answers/47454.htm).  The answer record basically tells you that you have to declare the Verilog component in VHDL.

 

The answer record also says that they will revisit this types of mixed-language issues if there are enough requests in the future.

 

I still have my Webcase open, and am asking which version of VHDL Vivado uses since I can't find it listed anywhere.  I'll post the answer if I get anything back.

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Visitor ed_xilinx
Visitor
14,155 Views
Registered: ‎07-02-2013

Re: vhdl-93 in vivado

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I had the same synthesis error
ERROR: [Synth 8-2396] near character '0' ; 3 visible types match here
related to the use of a constant '0' in the port map,

That was "only" due to the corresponding vhdl file missing in the project !
Of course Vivado gave me this strange error message instead of simply reported for the missing file ...
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Visitor dak_zach
Visitor
14,105 Views
Registered: ‎06-21-2013

Re: vhdl-93 in vivado

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I got the VHDL version currently supported in Vivado from the Webcase.  Vivado 2013.2 currently supports VHDL IEEE-STD-1076-1993 as well as floating and fixed point packages from VHDL 200x.   Hope that helps out someone in the future.

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Participant typhoonwa
Participant
13,729 Views
Registered: ‎06-09-2010

Re: vhdl-93 in vivado

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I have a very similar problem in Vivado 2013.2 but can't solve it in the way described above. Specifically, I have an IP block (a FIFO queue) which doesn't get recognized by the tool. I get the error:

 

[Synth 8-493] no such design unit 'input_queue'


Despite the fact that I have declared the component:

 

COMPONENT kvs_ht_FIFO_Hash_FuncIn97
  PORT (    clk     : IN STD_LOGIC;
            rst     : IN STD_LOGIC;
            din     : IN STD_LOGIC_VECTOR(96 DOWNTO 0);
            wr_en   : IN STD_LOGIC;
            rd_en   : IN STD_LOGIC;
            dout    : OUT STD_LOGIC_VECTOR(96 DOWNTO 0);
            full    : OUT STD_LOGIC;
            empty   : OUT STD_LOGIC);
END COMPONENT;

 

and instantiate correctly:

 

     input_queue : kvs_ht_FIFO_Hash_FuncIn97
       port map (clk    => clk,
                 rst    => rst,
                 din    => buffInData,
                 wr_en  => resizeValidArray(X),
                 rd_en  => funcInReady(X),
                 dout   => funcInData(X),
                 full   => buffFull(X),
                 empty  => buffEmpty(X));

 

am I missing something here? Or is it some limitation in Vivado synthesis?

 

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13,524 Views
Registered: ‎10-04-2013

Re: vhdl-93 in vivado : Zync and MicroZed

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I am trying to get a MicroZed board up and running with Vivado 2013.2.

I have VHDL as the primary flow language, but the heirarchy is showing Verilog GND component with red question mark.

Synthesis is moaning and strips the design out.

This sounds like the same problem.

Can anybody verify this please?

( Incidentally : dont try the spell checker here ! it doesnt even know VHDL or Vivado!)

 

Mike

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Visitor kaustin87
Visitor
12,880 Views
Registered: ‎04-02-2014

Re: vhdl-93 in vivado : Zync and MicroZed

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I am running into this same error in Vivado 2013.4 with the PCS/PMA IP for 10GbE:

 

  • [Synth 8-493] no such design unit 'ten_gig_eth_pcs_pma_wrapper' [ten_gig_eth_pcs_pma_v4_1.vhd:305]

The VHDL file is encrypted, and so is the wrapper. I added all the files manually to an RTL project. The files are included as sources. Any help would be appreciated.

 

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Xilinx Employee
Xilinx Employee
12,860 Views
Registered: ‎11-28-2007

Re: vhdl-93 in vivado : Zync and MicroZed

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Hi Kaustin87,

 

could you create a new thread? This thread is about Zynq and MicroZed in Vivado

When you do, can you report what error you are seeing?

 

In general, when working with IP in Vivado, you need to add the .XCI IP file, not the IP HDL sources.

The XCI will tell Vivado what the HDL files are, what libraries are used, which constraints and make a difference between HDL files for synthesis and files for simulation.

See UG896

 

 

Best regards,

Dries

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Visitor hbaier
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10,935 Views
Registered: ‎11-22-2008

Re: vhdl-93 in vivado

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This problem

 

ERROR: [Synth 8-2396] near character '0' ; 3 visible types match here
ERROR: [Synth 8-493] no such design unit: blk

 

and the problem with  instantion  inst : entiy work.xxxx

 

are all caused if you have in the module you want to instatiate 

 

use work.all;

 

I fighted for almost 20 hours until I removed use work.all from the modules.

 

--Heinz

 

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Visitor penkovsky
Visitor
10,061 Views
Registered: ‎10-15-2014

Re: vhdl-93 in vivado

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Thanks for the tip, hbaier. Indeed, I had to remove "use work.all;" statements and manually include all the modules. Somethingis terribly wrong with Vivado :(

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Visitor hbaier
Visitor
10,051 Views
Registered: ‎11-22-2008

Re: vhdl-93 in vivado

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and thank for your reponds

:-)

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