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Anonymous
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vhdl-93 in vivado

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Does anybody know how to set the vhdl-93 option in Vivado 2013.1 ?

In ISE, there was the possibility to set the "VHDL Source Analysis Standard" property to "VHDL-93".

In Vivado, I didn't find any way to set this option.

Unfortunately ISE is not an option because I have a gated clock design, which I need to translate with
the "gated_clock_conversion" option, which is only available in Vivado.

 

So does anybody know how to set the vhdl-93 option in Vivado ?

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Advisor
Advisor
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Registered: ‎02-12-2013

Hello,

 

What is the conclusion of the original thread?

 

I get the error below.  I see no solution in this thread. Please someone help.

 

ERROR: [Synth 8-2396] near character '0' ; 3 visible types match here

 

Here is my code snippet.

 

    sine_gen_inst: entity work.sine_gen
    Port map(
        reset         => '0', -- this causes the error.
        clk           => clk,
        --
        next_data     => tx_next_data,
        i_data        => sine_i_data,
        q_data        => sine_q_data);

 

 

 

 

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DSP in hardware and software
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Advisor
Advisor
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Registered: ‎02-12-2013
I should have posted the full error message. It shows the synthesis tool going through several libraries finding different definitions of '0'.

ERROR: [Synth 8-2396] near character '0' ; 3 visible types match here [/path/design_name.vhd:115]
INFO: [Synth 8-1047] first match for ''0'' found here [./vhdl_packages/1993/src/standard.vhd:11]
INFO: [Synth 8-1047] another match for ''0'' found here [./vhdl_packages/1993/src/standard.vhd:20]
INFO: [Synth 8-1047] another match for ''0'' found here [./vhdl_packages/1993/src/std_1164.vhd:22]


I think it is a bug in the compiler.
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DSP in hardware and software
-----------------------------------------
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Advisor
Advisor
4,939 Views
Registered: ‎02-12-2013
Actually, now I see what is happening here. I had not yet included my sine_gen module into the source list. Because of that the compiler did not yet know what type to use for the literal '0'.

It is a funny error message but now I know what to look for when I see it. Thanks.
----------------------------------------
DSP in hardware and software
-----------------------------------------
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Historian
Historian
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Registered: ‎02-25-2008

@pedro_uno wrote:
I should have posted the full error message. It shows the synthesis tool going through several libraries finding different definitions of '0'.

ERROR: [Synth 8-2396] near character '0' ; 3 visible types match here [/path/design_name.vhd:115]
INFO: [Synth 8-1047] first match for ''0'' found here [./vhdl_packages/1993/src/standard.vhd:11]
INFO: [Synth 8-1047] another match for ''0'' found here [./vhdl_packages/1993/src/standard.vhd:20]
INFO: [Synth 8-1047] another match for ''0'' found here [./vhdl_packages/1993/src/std_1164.vhd:22]



Ah, a clue:

 

INFO: [Synth 8-1047] first match for ''0'' found here [./vhdl_packages/1993/src/standard.vhd:11]

 

VHDL-93 did not allow using literals as the actuals in a port map. That was added in the 2002 update of the language. So if the synthesizer is following the strict VHDL-93 syntax, it should not even bother trying to determine the type of the actual. It should just error out.

 

Can Vivado be used in a VHDL-2002 or 2008 mode? That should work.

 

----------------------------Yes, I do this for a living.
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Explorer
Explorer
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Registered: ‎09-13-2011

ERROR: [Synth 8-2396] near character '0' ; 3 visible types match here [file.vhd:n]

 

Why isn't this error message fixed? It is highly misleading.

 

I came across it again in 2016.2 when I forgot a 'use' clause for a library with a component instantiation. It is the component that Vivado can't recognize, the type is not the problem.