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Visitor farhathsuj
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Registered: ‎12-06-2018

vhdl coding

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What is the meaning VHDL code line is ,Signal temp: std_LOGIC_VECTOR (31 downto 0) := (others => '0'); as iam new to VHDL programming…

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Contributor
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Registered: ‎04-06-2018

Re: vhdl coding

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you are just initializing the signal with 0 , zeros.

others=>'0' , say all vetor is filled with zeros.

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Contributor
Contributor
81 Views
Registered: ‎04-06-2018

Re: vhdl coding

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you are just initializing the signal with 0 , zeros.

others=>'0' , say all vetor is filled with zeros.

Visitor farhathsuj
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Registered: ‎12-06-2018

Re: vhdl coding

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tq or the reply,

function quantization_sgn(nbit : integer; max_abs : real; dval : real) return std_logic_vector is
variable temp : std_logic_vector(nbit-1 downto 0):=(others=>'0');
constant scale : real :=(2.0**(real(nbit-1)))/max_abs;
constant minq : integer := -(2**(nbit-1));
constant maxq : integer := +(2**(nbit-1))-1;
variable itemp : integer := 0;
begin
if(nbit>0) then
if (dval>=0.0) then
itemp := +(integer(+dval*scale+0.49));
else
itemp := -(integer(-dval*scale+0.49));
end if;
if(itemp<minq) then itemp := minq; end if;
if(itemp>maxq) then itemp := maxq; end if;
end if;
temp := std_logic_vector(to_signed(itemp,nbit));
return temp;

why 0.49 is used here..in this code ???
end quantization_sgn;

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