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Adventurer
Adventurer
305 Views
Registered: ‎08-04-2018

vivado 2016.4 - [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net design

Hi all,

 

I have this error. Can any one suggest me as to how do i have solve it.

This is the part of code I get the error in

bram_write: process(clk, command_done)
begin
--meas_data(20 downto 10) <= cmd_duration;
               
if (clk= '1') then
    if rst = '1' then
        s_m_bram_data <= x"00000000";
        s_m_bram_addr <= x"00000000";        
   else
   
       s_m_bram_addr <= s_m_bram_addr;
       s_m_bram_data<= s_m_bram_data;
   
   
   end if; 
--        ---meas_data <= meas_data;

    
    offset_value <= offset_value;
    
     
    if cmd_mode = PDCM then 
        meas_data(21 downto 10) <= meas_cmd_duration;   
        meas_data(1 downto 0) <= "01";
        if PDCM_cmd = DIS then 
            meas_data(3 downto 2) <= "00";
            offset_value <= "0000";
            --s_m_bram_en <= '1';         
        elsif PDCM_cmd = PDIS then
            meas_data(3 downto 2) <= "10";
            --s_m_bram_en <= '1';
            offset_value <= "0000";
        elsif PDCM_cmd = BRC then    
            meas_data(3 downto 2) <= "01";
            offset_value <= std_logic_vector(to_unsigned(five, offset_value'length));
        else
            offset_value <= offset_value;    
        end if;
    elsif cmd_mode = CRM then
        meas_data(21 downto 10) <= meas_cmd_duration;
        meas_data (1 downto 0) <= "10";
        if crm_data(28 downto 25) /= "1100" and crm_data(28 downto 25) /= "0000" then --just write type
            meas_data(3 downto 2) <= "00";
            offset_value <= std_logic_vector(to_unsigned(one, offset_value'length)); 
        elsif crm_data(28 downto 25) = "1110" then --- actual long CRM code, chang into 1110    --- change to crn_10bydata
            meas_data(3 downto 2) <= "10";
            offset_value <= std_logic_vector(to_unsigned(three, offset_value'length)); 
        elsif crm_data(28 downto 25) = "0000" then
            offset_value <= std_logic_vector(to_unsigned(two, offset_value'length));
            meas_data(3 downto 2) <= "01";
        --else
           -- offset_value <= offset_value;    
        end if;              
    else
        meas_data(21 downto 10) <= meas_cmd_duration;        
        meas_data (1 downto 0) <= "11";
    end if;
    
    meas_cmd_duration <= meas_cmd_duration;
    if rising_edge(command_done) then  
        if slave_read_trigger_i >"00" then
                wait_for_slave_response <= '1';
                wait_for_cmd <= '1';
                wait_for_meas <= '1';
                command_done_mode <= slave_read_trigger_i;    
        elsif slave_read_trigger_i ="00" then
            if cmd_mode= CRM then ---CRM
                wait_for_cmd <= '1';
                wait_for_meas <= '1';
                byte9to12 <= '1'; 
                byte5to8 <= '1';
                byte1to4 <= '1';
                meas_cmd_duration <= cmd_duration;
            elsif cmd_mode= PDCM then   ---PDCM 
                wait_for_slave_response <= '0';
                wait_for_cmd <= '0';
                wait_for_meas <= '1';
                meas_cmd_duration <= cmd_duration;           
            end if;                     
        end if;    
    end if;
    if i_slave_done = '1' then
        slave_done_mode <= '1';
        meas_cmd_duration <= cmd_duration;            
    end if;         
    bram_crm_10bydata <= crm_10bydata;
    --s_m_bram_addr <= s_m_bram_addr;
    bram_1response <= i_slave_data(151 downto 120);
    bram_2response <= i_slave_data(119 downto 88);
    bram_3response <= i_slave_data(87 downto 56);
    bram_4response <= i_slave_data(55 downto 24);
    bram_5response <= x"00" & i_slave_data(23 downto 0);
    if slave_done_mode = '1' then
        if wait_for_slave_response = '1' and wait_for_cmd = '1' and wait_for_meas = '1' then-- and i_slave_done='0' then
            base_addr <= base_addr;
            bram_crm_10bydata <= crm_10bydata;
            bram_crm_data <= crm_data;
            bram_slave_response <= i_slave_data;
            --bram_response_count <= bram_response_count;
            if command_done_mode = "10" then     
                s_m_bram_addr <= std_logic_vector(unsigned(base_addr) + 2); 
                --offset_value <= std_logic_vector(to_unsigned(two, offset_value'length));
                --base_addr <= std_logic_vector(unsigned(base_addr) +2);
                s_m_bram_data <= i_slave_data(32 downto 1);
                s_m_bram_en <= '1';
                wait_for_slave_response <= '0';
                wait_for_cmd <= '1';
                slave_done_mode <= '0';
                --meas_cmd_duration <= cmd_duration;
            elsif command_done_mode = "01" then
                --bram_response_count <= bram_response_count;
                if bram_response_count = 5 then
                    s_m_bram_addr <= std_logic_vector(unsigned(base_addr) + bram_response_count); 
                    --offset_value <= std_logic_vector(to_unsigned(one, offset_value'length));
                    --base_addr <= std_logic_vector(unsigned(base_addr) +2);
                    s_m_bram_data <= bram_1response;
                    s_m_bram_en <= '1';
                    wait_for_slave_response <= '1';
                    bram_response_count <= bram_response_count-1;
                    --wait_for_cmd <= '0';
                    --meas_cmd_duration <= cmd_duration;
                    bram_response_count <= bram_response_count-1;
                elsif bram_response_count = 4 then
                    s_m_bram_addr <= std_logic_vector(unsigned(base_addr) + bram_response_count); 
                    --offset_value <= std_logic_vector(to_unsigned(one, offset_value'length));
                    --base_addr <= std_logic_vector(unsigned(base_addr) +2);
                    s_m_bram_data <= bram_2response;
                    s_m_bram_en <= '1';
                    wait_for_slave_response <= '1';
                    bram_response_count <= bram_response_count-1;
                    --wait_for_cmd <= '0';
                    --meas_cmd_duration <= cmd_duration;
                    bram_response_count <= bram_response_count-1;
                elsif bram_response_count = 3 then
                    s_m_bram_addr <= std_logic_vector(unsigned(base_addr) + bram_response_count); 
                    --offset_value <= std_logic_vector(to_unsigned(one, offset_value'length));
                    --base_addr <= std_logic_vector(unsigned(base_addr) +2);
                    s_m_bram_data <= bram_3response;
                    s_m_bram_en <= '1';
                    wait_for_slave_response <= '1';
                    --wait_for_cmd <= '0';
                    --meas_cmd_duration <= cmd_duration;
                    bram_response_count <= bram_response_count-1;
                elsif bram_response_count = 2 then
                    s_m_bram_addr <= std_logic_vector(unsigned(base_addr) + bram_response_count); 
                    --offset_value <= std_logic_vector(to_unsigned(one, offset_value'length));
                    --base_addr <= std_logic_vector(unsigned(base_addr) +2);
                    s_m_bram_data <= bram_4response;
                    s_m_bram_en <= '1';
                    wait_for_slave_response <= '1';
                    --wait_for_cmd <= '0';
                    --meas_cmd_duration <= cmd_duration;
                    bram_response_count <= bram_response_count-1;
                elsif bram_response_count = 1 then
                    s_m_bram_addr <= std_logic_vector(unsigned(base_addr) + bram_response_count); 
                    --offset_value <= std_logic_vector(to_unsigned(one, offset_value'length));
                    --base_addr <= std_logic_vector(unsigned(base_addr) +2);
                    s_m_bram_data <= bram_5response;
                    s_m_bram_en <= '1';
                    wait_for_slave_response <= '0';
                    wait_for_cmd <= '0';
                    --bram_response_count <= 5;
                    --meas_cmd_duration <= cmd_duration;
                    bram_response_count <= bram_response_count-1;
                    slave_done_mode <= '0';
                end if;                                                                                                                    
            --else
               --s_m_bram_addr <= s_m_bram_addr; 
            end if;
        end if;            
    elsif wait_for_slave_response = '0' and wait_for_cmd = '1' and wait_for_meas = '1' then
        --offset_value<= offset_value;
        --if command_done_mode = "10" then 
            if crm_data(28 downto 25) /= "1110" then  ----- change to 1110
                s_m_bram_addr <=std_logic_vector(unsigned(base_addr) +1);
                --offset_value <= std_logic_vector(to_unsigned(one, offset_value'length));
                --base_addr <= std_logic_vector(unsigned(base_addr) +2);
                s_m_bram_data <= bram_crm_data;
                s_m_bram_en <= '1';
                wait_for_cmd <= '0';
            elsif crm_data(28 downto 25)= "1110" then  --- change to 1110
                s_m_bram_addr <= base_addr;
                s_m_bram_data <= s_m_bram_data;
                --offset_value <= std_logic_vector(to_unsigned(three, offset_value'length));
                if byte9to12 = '1' and byte5to8 = '1' and byte1to4 = '1' then   
                    s_m_bram_addr <= std_logic_vector(unsigned(base_addr) +3); 
                    --base_addr <= base_addr;
                    s_m_bram_data <= bram_crm_10bydata(96 downto 65);
                    s_m_bram_en <= '1';
                    byte9to12 <= '0';
                elsif byte9to12 = '0' and byte5to8 = '1' and byte1to4 = '1' then
                    s_m_bram_addr <= std_logic_vector(unsigned(base_addr) +2); 
                                            --base_addr <= std_logic_vector(unsigned(base_addr) +2);
                    s_m_bram_data <= bram_crm_10bydata(64 downto 33);
                    s_m_bram_en <= '1';
                    byte5to8 <= '0';
                elsif byte9to12 = '0' and byte5to8 = '0' and byte1to4 = '1' then    
                    s_m_bram_addr <= std_logic_vector(unsigned(base_addr) +1); 
                                            --base_addr <= std_logic_vector(unsigned(base_addr) +2);
                    s_m_bram_data <= bram_crm_10bydata(32 downto 1);
                    s_m_bram_en <= '1';
                    byte1to4 <= '0';
                    wait_for_cmd <= '0';            
                else
                    s_m_bram_data <= s_m_bram_data;
                    s_m_bram_addr <= base_addr;
                    s_m_bram_en <= '1';
                end if;
            else
                s_m_bram_data <= s_m_bram_data;
                s_m_bram_addr <= base_addr;
                s_m_bram_en <= '1';        
            end if;    
--        elsif cmd_mode = PDCM then
--            wait_for_cmd <= '0';
--            s_m_bram_addr <= base_addr;     
        --end if;    
    elsif wait_for_slave_response = '0' and wait_for_cmd = '0' and wait_for_meas = '1' then
        s_m_bram_addr <= base_addr;
        s_m_bram_data <= offset_value & meas_data(27 downto 0);
        s_m_bram_en <= '1';
        wait_for_meas <= '0';
        base_addr <= std_logic_vector(unsigned(base_addr) + unsigned(offset_value)+1);
        --meas_data(31 downto 28) <= offset_value;
    else
        s_m_bram_en <= '1';    
        s_m_bram_addr <= s_m_bram_addr;
        s_m_bram_data <= s_m_bram_data; 
        --base_addr <= base_addr;    
    end if;
    if s_m_bram_addr = not x"00000000" then
        s_m_bram_addr <= x"00000000";
    end if;       
-- else
--    --s_m_bram_en <= '0';    
--    s_m_bram_addr <= s_m_bram_addr;
--    s_m_bram_data <= s_m_bram_data; 
  --  base_addr <= base_addr; --<= std_logic_vector(unsigned(base_addr) + unsigned(offset_value)+1); 
    --end if;
end if;                                  
       
end process;
m_bram_en <= s_m_bram_en;
m_bram_addr <= s_m_bram_addr;
m_bram_data <= s_m_bram_data;
m_bram_we <= x"F";
--s_m_bram_addr <= base_addr;

 

 

Kindly help me. 

 

Thanks in advance

xilinx_1.JPG
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5 Replies
Moderator
Moderator
261 Views
Registered: ‎03-16-2017

Re: vivado 2016.4 - [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net design

Hi @benaka,

 

Lets look into the errors first. I will try to explain one of the error from it. 

Open synthesized design, and go to the net design_1/control_block_0/U0/byte1t04__0

And check that it has two drivers or not which are design_1_i/control_block_0/U0/byte1to4/Q   & design_1_i/control_block_0/U0/byte1to4_reg/Q.

Then, you need to make necessary changes into your RTL source code to drive this net with only one driver. 

Same, Do it for all the errors.

 

 

Regards,
hemangd

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Adventurer
Adventurer
252 Views
Registered: ‎08-04-2018

Re: vivado 2016.4 - [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net design

Hi @hemangd

 

I just found these, but I don't understand from where the second driver comes from. I have attached the screen shot for the same. Kindly let me know if its possible to clear without making any changes in the RTL level.. please

 

Thanks in advance

xili.PNG
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Moderator
Moderator
244 Views
Registered: ‎03-16-2017

Re: vivado 2016.4 - [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net design

Hi @benaka,

 

Can you provide your archived project to reproduce this issue at my end for further debugging purpose?

I have sent you ezmove ftp test package through which you can provide your files. 

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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Adventurer
Adventurer
237 Views
Registered: ‎08-04-2018

Re: vivado 2016.4 - [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net design

Hi @hemangd

I was trying to change the RTL a bit, and still encountered a similar error for the same part of the code. I have sent the zip file for the same.  

 

Thanks.

 

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Adventurer
Adventurer
221 Views
Registered: ‎08-04-2018

Re: vivado 2016.4 - [DRC 23-20] Rule violation (MDRV-1) Multiple Driver Nets - Net design

Hi @hemangd

 

So I managed to do a work around on the RTL level but now I have another issue.I first tried in the default way to generate the design, I got the timing warning and so tried the Flow_RunPhysOpt  method, still I get the error.

 

can you kindly have a look at this. Attached is the timing report for the same. 

xili.PNG
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