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Visitor yyaodesy
Visitor
759 Views
Registered: ‎05-04-2018

vivado 2017.1 stuck when xdma ip core is synthesising

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Dear All,

 

A problem encountered when I am synthesising my project which includes xdma core.

The Log information says:

 

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:04:48 ; elapsed = 00:05:17 . Memory (MB): peak = 1345.383 ; gain = 1011.527
Finished Timing Optimization : Time (s): cpu = 00:05:14 ; elapsed = 00:05:44 . Memory (MB): peak = 1534.066 ; gain = 1200.211
NDup read error: feof(1)
An unrecoverable error has occurred, synthesis cancelled.
TclStackFree: incorrect freePtr. Call out of sequence?

 

Also, I see a warning in Messages:

reset_run design_1_xdma_0_1_synth_1

[Vivado 12-1017] Problems encountered:
1. PID not specified

 =====================================================

I am working with Vivado 2017.1 and 64-bits windows 7 Enterprise. This problem happened suddenly (I mean, it still worked well yesterday.....)

Thanks for any help in advance!

 

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Visitor yyaodesy
Visitor
706 Views
Registered: ‎05-04-2018

Re: vivado 2017.1 stuck when xdma ip core is synthesising

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Problems solved by updating vivado to up-to-date version, 2018.02

Does it mean we should keep our vivado version up-to-date all the time? :-(

View solution in original post

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Visitor yyaodesy
Visitor
713 Views
Registered: ‎05-04-2018

Re: vivado 2017.1 stuck when xdma ip core is synthesising

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Also, I see some questions here: 

https://forums.xilinx.com/t5/Synthesis/WARNING-Vivado-12-1017-Problems-encountered-1-PID-not-specified/m-p/761738#M21370

 

BTW, Is there any possibility that this happened because of some updates on the OS Windows 7?

 

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Visitor yyaodesy
Visitor
692 Views
Registered: ‎05-04-2018

Re: vivado 2017.1 stuck when xdma ip core is synthesising

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I have tried to:

 

1) disable anti-virus sw;

2) reset .db outputs and restart synthesis;

3) delete redundant logic and constraint (even I have tried to synthesis a design only an xdma core inside...)

 

Still of no use...

Is there anybody can give me some advice?

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Visitor yyaodesy
Visitor
707 Views
Registered: ‎05-04-2018

Re: vivado 2017.1 stuck when xdma ip core is synthesising

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Problems solved by updating vivado to up-to-date version, 2018.02

Does it mean we should keep our vivado version up-to-date all the time? :-(

View solution in original post

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