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qunhuiv2pro
Visitor
Visitor
2,202 Views
Registered: ‎07-11-2017

vivado 2017.1 verilog synthesis weird syntax error

Hi I have an Arty 35T evaluation board and I downloaded vivado 2017.1 and installed with a valid license obtained with the product number. I tried several projects like GPIO, DDR3 memory, etc with Microblaze core, it worked Ok. When I tried to synthesize a piece of user  Verilog code, I had compile error message of a CORRECT always block: "always @(posedge Bus2IP_Clk) begin". The screen capture is attached below, and the signal is obvious already declared. Is this possibly a licensing problem?

 

Thanks a lot.

 

 

synthesis error.png
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4 Replies
hj
Moderator
Moderator
2,189 Views
Registered: ‎06-05-2013

Hi @qunhuiv2pro

 

 

Can you try to synthesize any example design if it works then please share the code I will try to run at my end. 

 

You can synthesize the belo FF code as well. 

 

module test(input clock,din,reset, output reg qout);

always @ (posedge clock)

if (reset)
qout<=0;
else
qout<=din;

endmodule

 

Thanks

HJ

 

 

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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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hbucher
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Registered: ‎03-22-2016

@qunhuiv2pro @hj

Out of curiosity, what is *before* the keyword "always" 

If you did not properly close a bracket or missed a module declaration it will spill out to the next statement.

 

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avrumw
Guide
Guide
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Registered: ‎01-23-2009

It is almost certainly NOT a licensing issue, but a real syntax error.

 

Based on the error message it is likely that the "always" is not legal syntax here. This would be the case if it were already inside an initial or always block (or a function or a variety of other syntax elements). So you need to look at the code before the "always" - the problem is there (and hence is not visible in your screen capture).

 

Avrum

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prathikm
Moderator
Moderator
2,123 Views
Registered: ‎09-15-2016

Hi @qunhuiv2pro,

 

You can check for proper termination and "usage" of always in your code. This should resolve the syntax issue.

If you can share the RTL we can have a look at that.

 

Thanks & Regards,
Prathik
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