02-15-2018 09:22 AM
Support for Verilog hierarchical pathnames in 2017.4 does not work!!!
See the video below - it is apparently a new feature in 2017.3, but in 2017.4 the following verilog code in a .sv file does not hook up properly.
If you elaborate this piece of RTL it DOES NOT hook up properly. If you synthesize it the correct netlist is created.
This is hopeless!!
module ins ( inp , outp1 , outp2) ;
input inp ;
output outp1 ;
output outp2 ;
wire trash ;
assign trash = inp ;
assign outp1 = ~inp ;
assign outp2 = trash ;
module simon( top_inp, top_outp, top_outp2 ) ;
input top_inp ;
output top_outp, top_outp2 ;
ins ins1 ( .inp(top_inp) , .outp1(top_outp) );
assign top_outp2 = ins1.trash ;
02-15-2018 02:39 PM
I didn't watch the video, but yikes, UG901 (2017.4) DOES indicated "Hierarchical names" as "Supported". But no examples are given. I wonder what Xilinx thinks this is?
I remember a few forums post indicating the desire for such a feature. Myself, I can think that it might be useful for debug only (I'm think it'll make chipscope ILA insertion easier). But actual use in a design flow? Can quickly lead the unmaintainable spaghetti-code if left in the wrong hands...
Interesting note, count me in as someone who wants to know more...
02-16-2018 02:49 AM
Thanks for your reply. Hierarchical path names are useful for debug as you mention. Typical situations are when you want to hook into a low level module from a top level wrapper - often to observe internal features using IO pins. Often you can use chipscope/ILA, or a third party tool such as Exostiv, to do this but sometimes you may wish to use an external logic analyzer.
Hierarchical path names allow you to push a debug bus into the hierarchy.
Our ASIC designs ( that I implement on FPGA for emulation ) also contain debug registers which monitor internal data flows between functional blocks. These debug registers can be read by one of the processors onboard. So sometime I will temporarily "borrow" a debug register and hook it up to a dodgy bit of logic so I can check out whats happening when we run code on the design. Doing this using hierarchical path names is obviously easier than pushing a new debug bus around a complex hierarchy.
I often build extremely "full" devices e.g. 85% or more utilisation for ASIC to FPGA flow. These designs take many hours (15!) to place and route and are very sensitive to disturbance from additional logic such as ILA. Working place and route strategies fail to meet timing and I have to respin the place and route again with different params. Again having the ability to use hierarchical path names minimises disruption to the design.