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tishi
Visitor
Visitor
1,008 Views
Registered: ‎02-12-2019

vivado add extra CARRY4

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The vivado add extra CARRY4

in h264/h265 cabac decoding there is one 9bit substract operation ivlCurrRange - lpsRange,
where the highest bit of ivlCurrRange is always 1, and the highest bit of lpsRange is always 0,
actually two CARRY4 is necessary for this substraction, the highest bit of output is the output of CO[3] of the second CARRY4,
I use 8 LUT2 and 2 CARRY4 to build up the module, the code is below,
after synthesize, vivado add an extra 1 CARRY4 which is totally unncessary,
why it OPTIMIZE to add extra thing, which do increase the path delay, how can I remove this extra CARRY4

 


`timescale 1ns / 10ps // timescale time_unit/time_presicion


module cabac_decode_bin
(
input wire [7:0] a,
input wire [7:0] b,
output wire [8:0] c
);


wire [7:0] same;
wire [7:0] co;
LUT2 #(.INIT(4'b1001)) lut2_1
(
.I0(a[0]),
.I1(b[0]),

.O(same[0])
);

LUT2 #(.INIT(4'b1001)) lut2_2
(
.I0(a[1]),
.I1(b[1]),

.O(same[1])
);

LUT2 #(.INIT(4'b1001)) lut2_3
(
.I0(a[2]),
.I1(b[2]),

.O(same[2])
);

LUT2 #(.INIT(4'b1001)) lut2_4
(
.I0(a[3]),
.I1(b[3]),

.O(same[3])
);

CARRY4 carry
(
.CI(1'b0),
.CYINIT(1'b1),
.DI(a[3:0]),
.S(same[3:0]),
.CO(co[3:0]),
.O(c[3:0])
);

LUT2 #(.INIT(4'b1001)) lut2_5
(
.I0(a[4]),
.I1(b[4]),

.O(same[4])
);

LUT2 #(.INIT(4'b1001)) lut2_6
(
.I0(a[5]),
.I1(b[5]),

.O(same[5])
);

LUT2 #(.INIT(4'b1001)) lut2_7
(
.I0(a[6]),
.I1(b[6]),

.O(same[6])
);

LUT2 #(.INIT(4'b1001)) lut2_8
(
.I0(a[7]),
.I1(b[7]),

.O(same[7])
);

CARRY4 carry2
(
.CI(co[3]),
.CYINIT(1'b0),
.DI(a[7:4]),
.S(same[7:4]),
.CO(co[7:4]),
.O(c[7:4])
);

assign c[8] = co[7];

endmodule

module test(
input wire clk,
input wire [7:0] A,
input wire [7:0] B,
output reg[8:0] C
);
reg [7:0] aa;
reg [7:0] bb;
wire [8:0] cc;

always @(posedge clk)
begin
aa<=A;
bb<=B;
C<=cc;
end


cabac_decode_bin cabac_inst
(
.a(aa),
.b(bb),
.c(cc)
);

endmodulecarry4.jpg

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1 Solution

Accepted Solutions
viviany
Xilinx Employee
Xilinx Employee
833 Views
Registered: ‎05-14-2008

Try the following and see if any change?

1. apply keep_hierarchy on module cabac_decode_bin

2. Use a separate wire name for co[7] and apply dont_touch on it.

(*dont_touch = "true"*) wire test_wire;

CARRY4 carry2
(
.CI(co[3]),
.CYINIT(1'b0),
.DI(a[7:4]),
.S(same[7:4]),
.CO(co[7:4]),
.O({test_wire, c[6:4])
);

assign c[8] = test_wire;

-vivian

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9 Replies
drjohnsmith
Teacher
Teacher
991 Views
Registered: ‎07-09-2009
Good question, and I don't know ...,

so this is a useless answer, but

Why are you using such low level design, the tools are optimised for using a higher level of abstraction,
for interest , what happens if you designed this using inference ?

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
viviany
Xilinx Employee
Xilinx Employee
962 Views
Registered: ‎05-14-2008

Is it still there if you run it through Implementation?

Which device are you using?

You can analyze the placement of these cells and see if it is necessary for sake of placement or routability.

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------
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tishi
Visitor
Visitor
920 Views
Registered: ‎02-12-2019
I am doing this to save one CARRY4 to meet 150M frequency in my H.265 desining.
The device I am using is ZYNQ7020.
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tishi
Visitor
Visitor
918 Views
Registered: ‎02-12-2019
The device I am using is ZYNQ7020.
After implement, the extra CARRY4 is still there.
You can see the extra CARRY4, the only input is CI , all other inputs is zero, it's totally unnecessary.
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drjohnsmith
Teacher
Teacher
886 Views
Registered: ‎07-09-2009
Have you tried inferring ?
an 9 bit subtraction at 150 MHz in the zynq is well within the range expected,
As to why the extra carry has been added, who knows, what are your timing constraints ? remember the tools run till your constraints are meet,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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tishi
Visitor
Visitor
870 Views
Registered: ‎02-12-2019
What do you mean inferring? like below?
wire [8:0] a;
wire [8:0] b;
wire [8:0] c;
assign c=a-b;
The substraction is only a little part of the whole critical path.


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drjohnsmith
Teacher
Teacher
852 Views
Registered: ‎07-09-2009
sorry was working on your comment " one 9bit substract operation ivlCurrRange - lpsRange"

yep basically as you say above
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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viviany
Xilinx Employee
Xilinx Employee
834 Views
Registered: ‎05-14-2008

Try the following and see if any change?

1. apply keep_hierarchy on module cabac_decode_bin

2. Use a separate wire name for co[7] and apply dont_touch on it.

(*dont_touch = "true"*) wire test_wire;

CARRY4 carry2
(
.CI(co[3]),
.CYINIT(1'b0),
.DI(a[7:4]),
.S(same[7:4]),
.CO(co[7:4]),
.O({test_wire, c[6:4])
);

assign c[8] = test_wire;

-vivian

-------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
如果您认为帖子有帮助,请点击“奖励”。谢谢!
-------------------------------------------------------------------------------------------------

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tishi
Visitor
Visitor
789 Views
Registered: ‎02-12-2019
Thanks, it works.
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