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Observer flydrive
Observer
192 Views
Registered: ‎09-10-2016

vivado synthesis internal signal naming

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When you open a synthesized design all the internal nets and leaves have generated names which are of a consistent format, eg grabbing one from a recent synthesis, ser_num_q_reg[8]_i_1_n_3. It's obvious what the start of it is, bit 8 of the ser_num_q register and this signal is one of those in the logic which determines the next value for the FDRE at the end. However does the suffix "_i_1_n_3" follow a pattern which is documented somewhere or is this purely an internal implementation detail of vivado? If it is documented, where? 

 

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Xilinx Employee
Xilinx Employee
161 Views
Registered: ‎05-22-2018

Re: vivado synthesis internal signal naming

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Hi @flydrive,

Nets, pins, and cells are hierarchical objects. They will be located in the hierarchy as defined by the RTL code, as long as hierarchy isn't flattened.

Tool internally add suffix accordingly for analyzing. I don't thing there is any specific document available defining the suffix for the names.

But there are some general ones for example which tool adds for his understanding:

  1. Port inputs have the prefix "i_"
  2. Port outputs have the prefix "o_"
  3. Port bi-directional pins have the prefix "io_"

Thanks,

Raj

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Xilinx Employee
Xilinx Employee
162 Views
Registered: ‎05-22-2018

Re: vivado synthesis internal signal naming

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Hi @flydrive,

Nets, pins, and cells are hierarchical objects. They will be located in the hierarchy as defined by the RTL code, as long as hierarchy isn't flattened.

Tool internally add suffix accordingly for analyzing. I don't thing there is any specific document available defining the suffix for the names.

But there are some general ones for example which tool adds for his understanding:

  1. Port inputs have the prefix "i_"
  2. Port outputs have the prefix "o_"
  3. Port bi-directional pins have the prefix "io_"

Thanks,

Raj

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Observer flydrive
Observer
104 Views
Registered: ‎09-10-2016

Re: vivado synthesis internal signal naming

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ok thanks for that - at least I didn't miss a piece of documentation and I'm not surprised this is just an internal implementation detail. 

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