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chant_yyy
Visitor
Visitor
1,566 Views
Registered: ‎04-11-2019

vivado synthesis results zero LUT,FF,DSP,BRAMs

[vivado] when I successfullly synthesized a design,I find the report shows it use zeos LUT,FF,DSP,BRAMS.In brief,it dosen't use any hardware resources on chip.And I find that input wires don't connet to the system in synthesis schematic. But in RTL schematic they do connect to the system, no wire is disconnected or hanging, what's the problem?

when I program the bitstream on chip, only the output wires work, and no signal input.image.png

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4 Replies
hemangd
Moderator
Moderator
1,564 Views
Registered: ‎03-16-2017

Hi @chant_yyy ,

It may possible that your logic has trimmed or removed by the synthesis tool. Check synthesis log in detail it will show critical warnings/warnings related to it. 

 

Also you may use Dont_touch attribute on those nets/signals/cells in your RTL source code which are trimmed/removed. For more info. on it check UG 901. synthesis User guide

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
hemangd
Moderator
Moderator
1,496 Views
Registered: ‎03-16-2017

Hi @chant_yyy ,

Is your issue resolved? If yes, then please close the thread by marking it as accepted solution. So community remain healthy.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
1,268 Views
Registered: ‎07-05-2018

Have you solved your problem?

1,197 Views
Registered: ‎07-05-2018

I was wondering this problem is caused by PHY IP in block design.