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001fd09138e7
Visitor
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Registered: ‎12-14-2015

wait constructs

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Hi, can someone tell me what types of VHDL wait constructs does Xilinx synthesis tool support?

 

II have verified that the wait ... until statement is synthesizable if a clock signal is used. But, for example, the wait on statement can be simulated, but it can not be synthesized. For example, the following code is not synthesizable:

 

library ieee;
use ieee.std_logic_1164.all;

 

entity AND_2e is
  port (a,b : in std_logic;
  f : out std_logic);
end AND_2e;

 

architecture Behavioral of AND_2e is
begin
process
begin
  wait on a,b;
  f <= a and b;
end process;
end Behavioral;

 

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001fd09138e7
Visitor
Visitor
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Registered: ‎12-14-2015

Hi, I know 4 different ways to use the reserved word wait in a process without a sensitivity list:

Wait until ...;
Wait on ...;
Wait for ...;
Wait;
I know that wait for  and wait can only be used in simulation and they are not implementable in an FPGA. But my question is if when I describe a code using a process without a list of sensitivity in which I put a wait until statement or a wait on statement, that code is implementable in an FPGA?. I have checked that the Xilinx synthesizer lets you simulate a code with a wait until statement, but I have not been able to implement anything using a wait until or a wait on statement. And I would like to know if it is possible or not.

 

I have tested with very simple circuits using wait until and wait on statements such as a flip-flop D, but I have not been able to implement them in an FPGA using those statements. I know how to implement those circuts by describing them without using such statements. My interest is to know if it is possible to use the wait until and wait on statements in implementable code in an FPGA

I apologize for my English

 

Thank you very much

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

@001fd09138e7 actually in the example you show, there is no reason to use "wait on" as the process already depends on any change in the variables ie process(a,b) f <= a and b; does exactly the same thing.

 

It is surprising to me that "wait until" is synthesizable in any case whether in a clocked process or not. Can you show your exact code?

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001fd09138e7
Visitor
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Registered: ‎12-14-2015

Hello, I used that example to check if the Xilinx synthesizer was able to synthesize a wait on statement. Obviously to implement an and gate it is not necessary to use a process nor a wait on instruction.
  I think there has been a misunderstanding. I have been able to synthesize a D flip-flop using a wait ... until statement, but I have not been able to implement it. The code I used is the following:

 

library ieee;
use ieee.std_logic_1164.all;

entity FFD is
  port (clk, d : in std_logic;
           Q : out std_logic);
end FFD;

architecture Behavioral of FFD is
begin
process
begin
   wait until rising_edge(clk);
   Q <= d;
end process;
end Behavioral;

 

My question remains the same, if it is used a wait statement in any of its versions, the code is synthesizable or not?

 

Thank you very much

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muzaffer
Teacher
Teacher
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Registered: ‎03-31-2012

@001fd09138e7 I guess I should've clarified my statement to say "except to infer a clock". Your usage of wait until rising edge is not common but it works. But you usually can't wait on any other signal and expect it be synthesized. Basically you can have a single wait-until statement to infer a register and this should be synthesizable. Any other usage would not be.

 

In any case, the following is the common way to define a register:

 

process (Clock, Reset)
begin
  if Reset = '0' then
    -- reset register, Q <= 0
  elsif RISING_EDGE(Clock) then
    -- increment register, Q <= Q + 1;
  end if;
end process;
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001fd09138e7
Visitor
Visitor
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Registered: ‎12-14-2015

Hi, I know 4 different ways to use the reserved word wait in a process without a sensitivity list:

Wait until ...;
Wait on ...;
Wait for ...;
Wait;
I know that wait for  and wait can only be used in simulation and they are not implementable in an FPGA. But my question is if when I describe a code using a process without a list of sensitivity in which I put a wait until statement or a wait on statement, that code is implementable in an FPGA?. I have checked that the Xilinx synthesizer lets you simulate a code with a wait until statement, but I have not been able to implement anything using a wait until or a wait on statement. And I would like to know if it is possible or not.

 

I have tested with very simple circuits using wait until and wait on statements such as a flip-flop D, but I have not been able to implement them in an FPGA using those statements. I know how to implement those circuts by describing them without using such statements. My interest is to know if it is possible to use the wait until and wait on statements in implementable code in an FPGA

I apologize for my English

 

Thank you very much

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