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Visitor yinbinjun
Visitor
965 Views
Registered: ‎12-10-2018

waring [Synth 8-327] inferring latch for variable 'next_s_reg'

reg   [3:0]     curr_s;        		//FSM current state
reg   [3:0]     next_s;        		//FSM next state

always @(posedge clk_r or negedge rst_n)
begin
    if(!rst_n)
        curr_s <= idle_s;
    else  begin 
        curr_s <= next_s;
    end
end
// FSM second level
always @(*)
begin
    case (curr_s)
            idle_s    : begin
                        if( PS2PL_signal[2:0] == 3'b001 )	
                            next_s = load_BN_s; // waring inferring latch
                        else if( PS2PL_signal[2:0] == 3'b010 )
                            next_s = load_WF_s;
                        else next_s = idle_s; 					
                    end
            load_BN_s : begin 
                        if( loadBN_cnt == ParaLoadBN )  
                            next_s = load_WF_s;
                        else next_s = load_BN_s;         							
                    end	
            load_WF_s : begin 
                         if( loadWF_cnt == ParaLoadWF ) 
                             next_s = calc_AB_s;
                         else next_s = load_WF_s;                                     
                    end          			
            calc_AB_s : begin
			 if( DMA_cnt < ParaAllOutMapDMA && conv_cnt == ParaCNNCalc )
				next_s = calc_BA_s;
                         else if( DMA_cnt == ParaAllOutMapDMA && conv_cnt == ParaCNNCalc) 
				next_s = idle_s;
			 else next_s = calc_AB_s;      
                    end 
            calc_BA_s : begin 
			 if( DMA_cnt < ParaAllOutMapDMA && conv_cnt == ParaCNNCalc )
				next_s = calc_AB_s;
                         else if( DMA_cnt == ParaAllOutMapDMA && conv_cnt == ParaCNNCalc) 
				next_s = idle_s;
			 else next_s = calc_BA_s;                          
                    end	
        default   next_s <= idle_s;
    endcase		
end		

 

 

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8 Replies
Scholar drjohnsmith
Scholar
953 Views
Registered: ‎07-09-2009

Re: waring [Synth 8-327] inferring latch for variable 'next_s_reg'

try defining defining state machines as a single item, not a clocked and a none clocked process,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Visitor yinbinjun
Visitor
950 Views
Registered: ‎12-10-2018

Re: waring [Synth 8-327] inferring latch for variable 'next_s_reg'

you mean that I need to split the state machine?

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Visitor yinbinjun
Visitor
947 Views
Registered: ‎12-10-2018

Re: waring [Synth 8-327] inferring latch for variable 'next_s_reg'

you mean that I need to split the state machine?
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Scholar drjohnsmith
Scholar
943 Views
Registered: ‎07-09-2009

Re: waring [Synth 8-327] inferring latch for variable 'next_s_reg'

the opposite, you currently have to parts, the clocked and the un clocked process,
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Scholar markcurry
Scholar
866 Views
Registered: ‎09-16-2009

Re: waring [Synth 8-327] inferring latch for variable 'next_s_reg'

I can't spot the latch - you look to have all conditions covered.  In any event, a catch-all solution to this is to always assign a "default" assignment near the beginning of your combinational procedural block 

// FSM second level
always @(*)
begin
   next_s = curr_s;  // Or some other "default" assignment -this "default" means when all else fails, stay in the same state.
   // add other state machine output "default" outputs here too 
   case (curr_s)
...

 

This suggestions is an alternative to drjohnsmith's suggestions of recoding as one always block.

Regards,

Mark

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Visitor yinbinjun
Visitor
851 Views
Registered: ‎12-10-2018

Re: waring [Synth 8-327] inferring latch for variable 'next_s_reg'

I have solved this problem
change
default next_s <= idle_s;
Visitor pclet
Visitor
517 Views
Registered: ‎01-27-2011

Re: waring [Synth 8-327] inferring latch for variable 'next_s_reg'

Hi

It's issued my code.

I don't understand your solution.

Please explain more specifically. 

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Moderator
Moderator
494 Views
Registered: ‎03-16-2017

Re: waring [Synth 8-327] inferring latch for variable 'next_s_reg'

Hi @pclet , 

You are asking a question on an old thread.

Please create a fresh new thread with your queries in detail and community will help you out asap.

Regards,
hemangd

Don't forget to give kudos and mark it as accepted solution if your issue gets resolved.
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