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Contributor
Contributor
12,012 Views
Registered: ‎10-11-2011

warning HDLCompiler:89

ise degsin suit 13.2, spartan 6 lx16

 i initiate a divider , and i got the warning:

HDLCompiler:89 - "E:\qiaodong\FPGA\test_FPGA\test_div\top.vhf" Line 53: <div_lx16> remains a black-box since it has no binding entity.

1. i just use the IP(CORE Generator & Architecture Wizard)=>divider generator, then i get the divider IP, and put it in the top.sch.

2. i can not simu the divider;

3. in the project, i instantiated 7 block rams and 3 floating-point ip use the same  method, and the other ips do not get this warning;

4. in spartan 3, i instantiated the divider use the same method, the warning did not show up;

 

 how can i fix this problem?

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15 Replies
Xilinx Employee
Xilinx Employee
12,009 Views
Registered: ‎08-17-2011

Re: warning HDLCompiler:89

Hello,

I'm assuming that's an issue in XST - if not please clarify.

Could you check you have all IO connected and that the xco file is used.

For example, for VHDL, check that in top .vhf the component and instantiation matches what is generated by Coregen and can be found in the vho file. Similar steps apply for Verilog.

Until you get the black box issue resolved you can't do simulation.

 

- Hervé

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Contributor
Contributor
11,996 Views
Registered: ‎10-11-2011

Re: warning HDLCompiler:89

hi , thanks for your time, i use the xst

this is  div_all_lx16.vho file:

 

your_instance_name : div_all_lx16
  port map (
   clk => clk,
   rfd => rfd,
   dividend => dividend,
   divisor => divisor,
   quotient => quotient,
   fractional => fractional);

 

this is top.vhf file:

 

   component div_all_lx16
      port ( clk        : in    std_logic;
             dividend   : in    std_logic_vector (18 downto 0);
             divisor    : in    std_logic_vector (9 downto 0);
             rfd        : out   std_logic;
             quotient   : out   std_logic_vector (18 downto 0);
             fractional : out   std_logic_vector (9 downto 0));
   end component;

 

      port map (clk=>dcm_40MHz,
                dividend(18 downto 0)=>dividend_all(18 downto 0),
                divisor(9 downto 0)=>divisor_all(9 downto 0),
                fractional(9 downto 0)=>fractional_all(9 downto 0),
                quotient(18 downto 0)=>quotient_all(18 downto 0),
                rfd=>open);

 

the rfd left open, does this cause the warning?

i instantiated 3 floating-point ip in the project, they also have open port, and they did not get the warning.

 

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Contributor
Contributor
11,992 Views
Registered: ‎10-11-2011

Re: warning HDLCompiler:89

i connect the "rdf" port and make it output, and the warning still there.

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Xilinx Employee
Xilinx Employee
11,983 Views
Registered: ‎07-16-2008

Re: warning HDLCompiler:89

Since only this divider IP gets this warning, you may compare it with other instantiations in top.vhf file. Any difference there?

 

Try to change the port mapping as the following.

 

   component div_all_lx16
      port ( clk        : in    std_logic;
             dividend   : in    std_logic_vector (18 downto 0);
             divisor    : in    std_logic_vector (9 downto 0);
             rfd        : out   std_logic;
             quotient   : out   std_logic_vector (18 downto 0);
             fractional : out   std_logic_vector (9 downto 0));
   end component;

 

      port map (clk=>dcm_40MHz,
                dividend(18 downto 0) => dividend_all (18 downto 0) ,
                divisor (9 downto 0) =>divisor_all (9 downto 0) ,
                fractional (9 downto 0) => fractional_all (9 downto 0) ,
                quotient (18 downto 0) =>quotient_all (18 downto 0) ,
                rfd=>open);

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Contributor
Contributor
11,980 Views
Registered: ‎10-11-2011

Re: warning HDLCompiler:89

hi grace:

    i have  compared, there are no difference;

    and i delete the (* downto *), it did not work, the warning still there.

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Xilinx Employee
Xilinx Employee
11,977 Views
Registered: ‎05-14-2008

Re: warning HDLCompiler:89

Do you add the .xco file of the divider core to the project? Did you generate the divider core in Verilog or VHDL?

 

What problem are you encountering during simulation?

 

Vivian

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Contributor
Contributor
11,961 Views
Registered: ‎10-11-2011

Re: warning HDLCompiler:89

hi viviany

      1.i add the .xco file;

      2. i use vhdl

      3.when i add a test bench and choose the top as the "associate file", i observe the divider's ports, and it works well, 

      4.when i add a test bench and choose the divider as the "associate file", it seems like the simulator can not find the divider, the port and its width are wrong.

      5.my project works well, so  it seems like the warning did not matter, but i still want to know why the warning occur and is there any potiental problem. and in spartan 3, i instantiated the divider use the same method, the warning did not show up;

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Xilinx Employee
Xilinx Employee
11,955 Views
Registered: ‎05-14-2008

Re: warning HDLCompiler:89

Does the warning occur during Synthesis or Simulation? What Simulator are you using, ISIM or any other 3rd party tool?

 

Vivian

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Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------------------------------
如果提供的信息能解决您的问题,请标记为“接受为解决方案”。
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Xilinx Employee
Xilinx Employee
11,954 Views
Registered: ‎05-14-2008

Re: warning HDLCompiler:89

Can you reproduce this issue in a simple test case and attach your test case here?

 

Vivian

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Contributor
Contributor
9,386 Views
Registered: ‎10-11-2011

Re: warning HDLCompiler:89

hi viviany:

 the warning occur during Synthesis, i build a simple project so everyone can see the detail;

 

description:

1. when i initated an dividor ,i got the warning :HDLCompiler:89

2. i can simu the top, and the dividor works well

3.i can not simu the dividor alone: when i add an testbench file and associate it to the dividor, it seems like the xst can not find the dividor

4. i use spartan 6 lx16, ise design suit 13.2, xst as the simulator

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Xilinx Employee
Xilinx Employee
9,378 Views
Registered: ‎08-17-2011

Re: warning HDLCompiler:89

hello,

With your provided project/example, I first got the same warning as you, but then I did regenerate the core, and on the second run the warnings disappeared.
Steps to regenerate the cores: in ISE select the xco then in the process plane, run "regenerate core".

-> Can you check that?
HTH
- Hervé

SIGNATURE:
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* Please mark the Answer as "Accept as solution" if information provided is helpful.
* Give Kudos to a post which you think is helpful and reply oriented.
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Contributor
Contributor
9,367 Views
Registered: ‎10-11-2011

Re: warning HDLCompiler:89

hi herver

   i regenerate the core and update the symbol, the warning still there...

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Highlighted
Newbie runhong
Newbie
9,059 Views
Registered: ‎09-21-2012

Re: warning HDLCompiler:89

I am facing the same problem. Please help. Thanks!

Tags (1)
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Visitor kwilhelm
Visitor
8,735 Views
Registered: ‎11-12-2012

Re: warning HDLCompiler:89

What version of ISE did you use? I'm running ISE 13.1 and I have the same problem as the OP. I found that if I go into the Coregen project and switch the Simulation Files option for Preferred Simulation Model from "Structural" to "Behavioral", the warning changes from the black-box warning to:

 

HDLCompiler:758 - "input_fifo.vhd" Line 43: Replacing existing netlist input_fifo()

 

 

I'm using a Spartan6 LX100. FIFO was generated using the Fifo Generator v8.1.

 

No matter what I do, I can't seem to get rid of getting one or the other of these two warnings. I have a rather large design going, and I'm getting this warning on almost every Coregen piece. It would be nice to know what is causing these warnings.

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Observer gumas
Observer
7,584 Views
Registered: ‎08-08-2013

Re: warning HDLCompiler:89

I also have this problem ( on ISE 16.6 ). Did anyone found a solution?

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